DCT

2:21-cv-00463

Netlist Inc v. Samsung Electronics Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:21-cv-00463, E.D. Tex., 05/03/2022
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants maintain a regular and established place of business in the district and have committed acts of infringement there.
  • Core Dispute: Plaintiff alleges that Defendant’s high-performance memory products, including DDR4, DDR5, and High Bandwidth Memory (HBM) modules, infringe six patents related to memory module architecture, timing control, and power management.
  • Technical Context: The technology at issue involves high-performance computer memory modules, which are essential components for data-intensive applications such as servers, cloud computing, and artificial intelligence.
  • Key Procedural History: The complaint notes a prior 2015 Joint Development and License Agreement (JDLA) between the parties, which Netlist alleges it terminated on July 15, 2020. This termination was subsequently found effective by a judgment in the Central District of California, which may be relevant to potential licensing defenses.

Case Timeline

Date Event
2007-06-01 Priority Date for '918 and '054 Patents
2009-07-16 Priority Date for '339 Patent
2010-11-03 Priority Date for '060 and '160 Patents
2012-07-27 Priority Date for '506 Patent
2014-07-22 '060 Patent Issued
2016-04-19 '160 Patent Issued
2020-07-15 Netlist terminates JDLA with Samsung
2020-12-08 '506 Patent Issued
2021-03-16 '339 Patent Issued
2021-05-25 '918 Patent Issued
2021-10-12 Samsung publicizes accused DDR5 products
2021-12-20 Initial Complaint Filed
2022-01-25 '054 Patent Issued
2022-05-03 First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,860,506 - "Memory Module With Timing-Controlled Data Buffering" (Issued Dec. 8, 2020)

The Invention Explained

  • Problem Addressed: The patent describes a problem in conventional high-speed memory modules where the distribution of control and clock signals is subject to "strict constraints" (’506 Patent, col. 2:16-20). Physically balancing the length of signal wires to ensure simultaneous signal arrival at all memory devices "compromises system performance, limits the number of memory devices, and complicates their connections" (Compl. ¶20; ’506 Patent, col. 2:24-27).
  • The Patented Solution: The invention proposes a memory module with multiple buffer circuits distributed across its surface, positioned near the memory devices they serve (’506 Patent, Fig. 2A). Each buffer circuit contains a delay circuit that can adjust the timing of data signals passing through it (’506 Patent, Abstract). This allows the system to compensate for the different travel times that control signals take to reach different buffer circuits across the module, particularly during high-speed operations where signals may take more than one clock cycle to traverse the board (Compl. ¶23; ’506 Patent, col. 9:51-62).
  • Technical Importance: This approach provides a mechanism for fine-grained timing control directly on the memory module, addressing signal integrity issues that become more acute as memory operating speeds and densities increase (Compl. ¶20; ’506 Patent, col. 2:32-36).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶66).
  • Claim 1 recites a memory module comprising: a module board; a module control device (e.g., an RCD); memory devices arranged in multiple ranks; and data buffers. The claim's key elements require a first data buffer to be configurable to:
    • delay a first read strobe by a first predetermined amount to generate a first delayed read strobe;
    • sample a first section of read data using the first delayed read strobe;
    • transmit the sampled data to the data bus; and
    • wherein the "first predetermined amount" of delay is determined based on signals received by the data buffer during "one or more previous operations." (’506 Patent, col. 19:46-20:5).
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 10,949,339 - "Memory Module With Controlled Byte-Wise Buffers" (Issued Mar. 16, 2021)

The Invention Explained

  • Problem Addressed: The patent notes the trade-offs in memory subsystem design between density, power dissipation, speed, and cost, explaining that "increasing memory density typically causes higher power dissipation, slower operational speed, and higher costs" (Compl. ¶26; ’339 Patent, col. 2:9-12).
  • The Patented Solution: The invention is a memory module designed to reduce the electrical load on the system's memory controller (’339 Patent, Abstract). It uses a plurality of "byte-wise buffers" that are controlled by a module controller. When a read or write operation targets a specific rank of memory, the buffer associated with that rank is enabled to act as a bidirectional repeater, while buffers for other ranks are disabled (’339 Patent, col. 17:23-32). This ensures the memory controller only "sees" the load of the single active buffer rather than the load of all memory devices, which "enhances the performance and reduces the power requirements of the memory system" (Compl. ¶29; ’339 Patent, col. 17:39-42).
  • Technical Importance: By isolating memory ranks and reducing the electrical load on the memory controller, the invention allows for higher performance and lower power consumption, particularly in systems with a high density of memory devices (Compl. ¶29).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶79).
  • Claim 1 recites an N-bit-wide memory module comprising: a printed circuit board (PCB) with an edge connector; DDR DRAM devices in multiple ranks; a module controller; and a plurality of "byte-wise buffers." The core elements require that each byte-wise buffer:
    • is coupled to the PCB and receives module control signals;
    • has a first side coupled to the external data bus and a second side coupled to DDR DRAM devices;
    • includes logic to control a byte-wise data path between the first and second sides;
    • the data path includes "first tristate buffers"; and
    • the logic is configured to "enable the first tristate buffers...to drive the respective byte-wise section of the N-bit wide write data to the respective module data lines during the first time period." (’339 Patent, col. 23:36-24:36).
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

Multi-Patent Capsules for Remaining Patents-in-Suit:

  • U.S. Patent No. 11,016,918: "Flash-DRAM Hybrid Memory Module," issued May 25, 2021.

    • Technology Synopsis: The patent addresses power management in memory modules. It describes moving voltage regulation functions from the motherboard onto the memory module itself, using multiple on-module buck converters to provide various regulated voltages to different components. This design allows for more precise voltage regulation and efficient power management, which is a key characteristic of the DDR5 memory standard (Compl. ¶¶32, 35-36).
    • Asserted Claims: At least one claim (Compl. ¶93).
    • Accused Features: The complaint accuses Samsung's DDR5 memory modules that utilize an on-module Power Management Integrated Circuit (PMIC) (Compl. ¶¶93, 95).

  • U.S. Patent No. 11,232,054: "Flash-DRAM Hybrid Memory Module," issued Jan. 25, 2022.

    • Technology Synopsis: As a continuation of the '918 Patent, this patent covers similar on-module power management technology. It discloses a memory module with first, second, and third buck converters that receive a pre-regulated input voltage and produce multiple regulated voltages for components like SDRAM devices, improving power efficiency for DDR5 modules (Compl. ¶¶39, 41).
    • Asserted Claims: At least one claim (Compl. ¶106).
    • Accused Features: The complaint accuses Samsung's DDR5 products featuring an on-DIMM PMIC (Compl. ¶¶106, 108).

  • U.S. Patent No. 8,787,060: "Method and Apparatus for Optimizing Driver Load in a Memory Package," issued Jul. 22, 2014.

    • Technology Synopsis: The patent addresses signal load issues in vertically stacked memory packages (like HBM). In conventional designs, data interconnects often connect to all stacked dies, increasing the electrical load. The invention discloses a memory package with multiple, separate die interconnects, where a first interconnect communicates with a first subset of array dies and a second interconnect communicates with a second subset, reducing the load on the data conduits (Compl. ¶¶45, 47).
    • Asserted Claims: At least claim 20 (Compl. ¶118).
    • Accused Features: The complaint accuses Samsung's HBM, HBM2, and HBM2E products, which feature vertically stacked DRAM dies (Compl. ¶¶61, 118).

  • U.S. Patent No. 9,318,160: "Memory Package with Optimized Driver Load and Method of Operation," issued Apr. 19, 2016.

    • Technology Synopsis: As a continuation of the '060 Patent, this patent discloses a similar solution for optimizing load in stacked-die memory packages. It describes a memory package where different die interconnects are in electrical communication with some, but not all, of the array dies, which lowers power consumption and allows for a smaller form factor (Compl. ¶¶45, 47-48).
    • Asserted Claims: At least claim 1 (Compl. ¶128).
    • Accused Features: The complaint accuses Samsung's HBM products that use stacked die technology (Compl. ¶¶61, 128).

III. The Accused Instrumentality

  • Product Identification: The complaint identifies the "Accused Instrumentalities" as a broad range of Samsung's memory products, including DDR4 LRDIMMs, various DDR5 DIMM formats (LRDIMM, RDIMM, SODIMM, UDIMM), and High Bandwidth Memory products (HBM2, HBM2E) (Compl. ¶54). Specific product families like "Flarebolt," "Aquabolt," and "Flashbolt" are named (Compl. ¶¶62-64).
  • Functionality and Market Context:
    • DDR4 LRDIMMs: These are Load-Reduced Dual In-line Memory Modules designed for servers. The complaint alleges they include a Registering Clock Driver (RCD) for command and control signals and separate data buffers to enhance data signals, thereby enabling high-density modules (Compl. ¶¶68, 70, 73). A marketing image depicts a Samsung DDR4 LRDIMM module with an RCD and nine data buffer chips visible on the PCB (Compl. Ex. 19 at 2).
    • DDR5 Memory Modules: A key accused feature of these products is an on-module Power Management Integrated Circuit (PMIC). This design integrates voltage regulation onto the DIMM itself, a departure from prior generations where the PMIC was on the motherboard. This allegedly provides more efficient power management and stability (Compl. ¶¶57, 95). A photograph shows a Samsung DDR5 RDIMM obtainable in the U.S. (Compl. ¶59).
    • HBM Products: These products use vertically stacked DRAM dies interconnected by Through-Silicon Vias (TSVs) to achieve high bandwidth in a small form factor. They are marketed for high-performance computing and AI applications (Compl. ¶¶61, 119). A representative product image depicts the stacked-die architecture of an HBM2E Flashbolt product (Compl. ¶64).

IV. Analysis of Infringement Allegations

'506 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a module control device...configurable to receive input C/A signals...and to output registered C/A signals...and to output module control signals The accused DDR4 LRDIMMs include a registering clock driver (RCD) that receives input command/address (C/A) signals and outputs registered C/A signals and module control signals. ¶70 col. 19:25-32
memory devices arranged in multiple ranks...wherein the registered C/A signals cause a selected rank...to perform the memory read operation The accused products' memory devices are arranged in multiple ranks, and the registered C/A signals from the RCD cause a selected rank to perform a read operation. ¶¶71, 72 col. 19:33-40
data buffers on the module board...wherein a first data buffer...is configurable to...delay the first read strobe by a first predetermined amount to generate a first delayed read strobe; The accused DDR4 LRDIMMs include data buffers with variable delay circuitry that delay the MDQS strobes to generate a first delayed read strobe. ¶¶73, 74 col. 19:46-60
sample the first section of the read data using the first delayed read strobe; and transmit the first section of the read data The data buffer samples the read data using the delayed strobe and transmits it to the data bus. ¶74 col. 19:61-20:1
wherein the first predetermined amount is determined based at least on signals received by the first data buffer during one or more previous operations. The data buffer determines the amount of delay based on signals (e.g., BCOM signals) received from the memory controller during previous operations, such as MRD training. ¶74 col. 10:11-21
  • Identified Points of Contention:
    • Technical Question: The central dispute may focus on the final limitation. The complaint alleges that the industry-standard Multi-Rank Read (MRD) training process used in the accused LRDIMMs constitutes determining a delay amount based on signals from "previous operations." A key question for the court will be whether the specific mechanism of MRD training, where the memory controller sends signals to the data buffer to calibrate timing, meets the functional requirements of this claim element.

'339 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a plurality of byte-wise buffers coupled to the PCB and configured to receive the module control signals The accused DDR4 LRDIMMs comprise a plurality of data buffers coupled to the PCB that receive module control signals from the RCD. A JEDEC diagram illustrates the topology of these buffers (Compl. Ex. 11). ¶86 col. 24:3-6
wherein each respective byte-wise buffer...has a first side...a second side...and a byte-wise data path Each buffer has a first side coupled to the data bus and a second side coupled to the DRAM devices, with a data path between them. A logic diagram illustrates this path (Compl. Ex. 9 at 95). ¶86 col. 24:7-12
wherein the each respective byte-wise buffer further includes logic configurable to control the byte-wise data path...and the byte-wise data path includes first tristate buffers Each buffer allegedly includes logic and tristate buffers to control the data path in response to module control signals. ¶87 col. 16:40-50
the logic...is configured to enable the first tristate buffers...to drive the respective byte-wise section of the N-bit wide write data to the respective module data lines during the first time period. The logic is configured to enable the tristate buffers (e.g., via an MDQ_OE signal) to drive write data from the memory controller to the DRAM devices during a write operation. ¶87 col. 24:26-36
  • Identified Points of Contention:
    • Scope Question: A potential point of contention is whether the accused "data buffers" in Samsung's LRDIMMs meet the definition of "byte-wise buffers" as that term is used in the patent. The analysis may turn on the specific internal architecture and functionality of the accused buffers compared to the embodiments described in the ’339 Patent specification.
    • Technical Question: Another question may be whether the logic in the accused products that enables the tristate buffers operates "in response to the module control signals" in the manner required by the claim, or if it operates in a technically distinct way.

V. Key Claim Terms for Construction

  • From the ’506 Patent: "predetermined amount is determined based at least on signals received by the first data buffer during one or more previous operations"

    • Context and Importance: This term is central to the infringement theory for the '506 Patent. The patentability of the claim may rest on this active, on-module timing calibration. Practitioners may focus on this term because its construction will determine whether a standard industry process like MRD training falls within the claim's scope.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes using a "time interval," determined during a write operation, to time a subsequent read operation, which suggests a functional concept not limited to a specific algorithm ('506 Patent, col. 10:11-21).
      • Evidence for a Narrower Interpretation: The patent discloses "signal alignment circuits" that perform this function ('506 Patent, col. 10:11-14). A defendant might argue this implies a specific circuit structure rather than just any process that achieves a similar result.

  • From the ’339 Patent: "byte-wise buffer"

    • Context and Importance: The identity of this structural element is a prerequisite for infringement. The dispute will likely involve whether Samsung's off-the-shelf data buffers, which serve a similar load-reducing purpose in an LRDIMM, are properly characterized by this term.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The abstract describes the buffers functionally as being "controlled by the set of module control signals to actively drive respective byte-wise sections of each data signal" (’339 Patent, Abstract). This could support an interpretation covering any buffer that performs this byte-level driving function.
      • Evidence for a Narrower Interpretation: The specification states that in certain embodiments, "each of the one or more data transmission circuits 416 has the same bit width as does the associated memory devices 412 per rank" (’339 Patent, col. 13:31-36). A defendant could argue this phrase limits the term to buffers with a specific bit-width relationship to the memory chips.

VI. Other Allegations

  • Indirect Infringement: For both the '506 and '339 patents, the complaint alleges inducement based on Samsung providing "specifications, datasheets, instruction manuals, and/or other materials that encourage and facilitate infringing use" of the accused products (Compl. ¶¶75, 89). It also alleges contributory infringement, asserting the accused products have "no substantial noninfringing use" and constitute a material part of the invention (Compl. ¶¶76, 90).
  • Willful Infringement: The complaint alleges that Samsung has had actual notice of the '506 and '339 patents since at least August 2, 2021, which predates the filing of the initial complaint. It alleges that Samsung’s infringement has been and continues to be willful, despite a high likelihood that its actions constitute infringement (Compl. ¶¶77, 91).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of functional equivalence: Does the industry-standard Multi-Rank Read (MRD) training protocol implemented in Samsung’s DDR4 LRDIMMs perform the specific function of determining and applying a timing delay based on signals from "previous operations," as required by Claim 1 of the '506 patent, or is there a fundamental mismatch in technical operation?
  • A second key question will be one of definitional scope: Can the term "byte-wise buffer," as defined by the intrinsic evidence of the '339 patent, be construed to cover the standardized data buffer components used in Samsung’s DDR4 LRDIMMs, or do differences in their specific implementation place them outside the scope of the claims?
  • A third issue will be the impact of industry standards: The accused products for the lead patents are DDR4 and DDR5 modules that allegedly comply with JEDEC standards. The case will likely explore the interplay between patented inventions and the implementation of these widely adopted industry standards, raising questions about whether practicing the standard necessarily results in infringement.