Mallard IP LLC v. Radisys Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Mallard IP LLC (Texas)
  • Defendant: Radisys Corporation (Oregon)
  • Plaintiff’s Counsel: Kent & Risley LLC
• Case Identification: 2:21-cv-00471, E.D. Tex., 12/29/2021
• Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains a regular and established place of business within the Eastern District of Texas.
• Core Dispute: Plaintiff alleges that Defendant’s DC Engine 16U System infringes a patent related to dynamically configurable digital circuit blocks used in microcontrollers and other integrated circuits.
• Technical Context: The technology concerns reconfigurable hardware architectures that aim to blend the flexibility of Field Programmable Gate Arrays (FPGAs) with the efficiency of application-specific circuits.
• Key Procedural History: The complaint does not mention any prior litigation, licensing history, or post-grant proceedings involving the patent-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,603,330 - “Configuring Digital Functions in a Digital Configurable Macro Architecture”

• Patent Identification: U.S. Patent No. 6,603,330, “Configuring Digital Functions in a Digital Configurable Macro Architecture,” issued August 5, 2003.

The Invention Explained

• Problem Addressed: The patent asserts that general-purpose Field Programmable Gate Arrays (FPGAs) are inefficient for many microcontroller applications due to high cost and wasted chip area, and that re-programming them to implement new functions is a "time consuming task" unsuitable for real-time processing (’330 Patent, col. 1:46-58).
• The Patented Solution: The invention is a "programmable digital circuit block" that is designed to be more efficient than an FPGA by being configurable to perform only one of a variety of predetermined digital functions, such as a timer, counter, or serial communication port (’330 Patent, Abstract). Configuration is achieved by changing the contents of a small number of "configuration registers," which allows the block to be "dynamically configurable from one predetermined digital function to another" for real-time applications (’330 Patent, col. 2:21-33). The architecture, shown in Figure 1, is based on reusing a common set of selectable logic circuits and data registers for multiple pre-defined tasks (’330 Patent, col. 5:42-56).
• Technical Importance: This architecture seeks to provide a middle ground between static, single-purpose hardware and fully programmable logic, offering reconfigurability for common tasks without the overhead of a general-purpose FPGA (’330 Patent, col. 2:1-12).

Key Claims at a Glance

• The complaint asserts independent method claim 25 (’330 Patent, col. 10:55-68; Compl. ¶15).
• The essential steps of claim 25 include:
  • loading a plurality of configuration data corresponding to any one of a plurality of predetermined digital functions into a configuration register of a programmable digital circuit block; and
  • configuring the programmable digital circuit block to perform any one of the plurality of predetermined digital functions based on the configuration data,
  • wherein these steps are dynamically performed, and
  • wherein the block includes a data register for storing data to facilitate performing the function.
• The complaint does not explicitly reserve the right to assert other claims.

III. The Accused Instrumentality

Product Identification

• The complaint identifies the accused instrumentality as Defendant’s “DC Engine 16U System” (Compl. ¶15).

Functionality and Market Context

• The complaint does not provide sufficient detail for analysis of the accused instrumentality's specific functionality, architecture, or market role. It is identified only by name (Compl. ¶15).

IV. Analysis of Infringement Allegations

The complaint alleges that Defendant infringes at least claim 25 of the ’330 Patent in connection with the DC Engine 16U System (Compl. ¶15). It states that this infringement is detailed in a "preliminary claim chart attached hereto as Exhibit B," but this exhibit was not filed with the complaint (Compl. ¶15). No probative visual evidence provided in complaint. Consequently, the specific factual basis for the infringement allegation is not articulated in the provided document.

• Identified Points of Contention: Lacking a detailed infringement theory from the Plaintiff, analysis of potential disputes must be inferred from the patent's claims and specification. Key questions may include:
  • Architectural Questions: Does the "DC Engine 16U System" contain a "programmable digital circuit block" as described in the patent, or is it a different architecture, such as a general-purpose CPU, a traditional FPGA, or a fixed-function Application-Specific Integrated Circuit (ASIC)? The patent’s emphasis on a specific architecture designed for a "plurality of predetermined digital functions" suggests that a mismatch at this foundational level could be a central issue.
  • Functional Questions: Assuming the accused system has a relevant architecture, what evidence demonstrates that it performs the method of claim 25? Specifically, does it "dynamically" reconfigure its hardware blocks during operation by loading data into "configuration registers" to switch between distinct, pre-defined functions?

V. Key Claim Terms for Construction

• The Term: "predetermined digital functions"

• Context and Importance: This term is central to the patent's asserted novelty over prior art FPGAs, which the patent characterizes as being programmable to perform "any arbitrary digital function" (’330 Patent, col. 3:59-62). The scope of "predetermined" will likely be a focal point, as it defines whether the accused device's capabilities fall inside or outside the claimed invention. Practitioners may focus on this term because if the accused device is found to be a general-purpose programmable device, it may not infringe.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent states that the blocks "can be configured, for example, as timers, counters, serial communication ports..." suggesting the list is not exhaustive (’330 Patent, col. 2:8-12). This may support an argument that "predetermined" refers to any function for which the block was designed, even if that set is large.
  • Evidence for a Narrower Interpretation: The specification repeatedly contrasts the invention with FPGAs, emphasizing that the circuit components are designed for reuse in "several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block" (’330 Patent, col. 3:62-65). This language may support a narrower construction where the functions must be a limited, specific set for which the hardware is optimized, not just any function that could be programmed.

• The Term: "dynamically performed"

• Context and Importance: This term in method claim 25 requires that the loading and configuring steps occur "dynamically." This is critical to the infringement analysis, as it relates to the real-time reconfigurability that the patent touts as an advantage over the "time consuming task" of re-programming FPGAs (’330 Patent, col. 1:53-56).

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent describes the configuration as "fast and easy" and states the block can be programmed "on-the-fly" (’330 Patent, col. 5:20-22). This could support a broad definition of "dynamically" as any reconfiguration that occurs during the device's operation, as opposed to only at initial power-on.
  • Evidence for a Narrower Interpretation: The context of "real-time processing" could suggest that "dynamically" implies a reconfiguration that happens in response to processing needs during a single, continuous operation (’330 Patent, col. 2:30-33). An argument could be made that a system that is merely reconfigured between distinct operational sessions, but not during one, does not perform the steps "dynamically."

VI. Other Allegations

The complaint does not contain allegations of indirect or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

Based on the complaint and the patent, the resolution of this dispute may turn on the following high-level questions:

1. A core architectural question: Can the "DC Engine 16U System" be properly characterized as containing the specific "programmable digital circuit block" claimed in the ’330 patent—an architecture optimized for a set of "predetermined" functions—or is it a fundamentally different type of device, such as a general-purpose processor or a conventional FPGA, that falls outside the patent's scope?
2. A key evidentiary question: Assuming an architectural match, what factual evidence will demonstrate that the accused system actually performs the method of claim 25? The case will likely depend on evidence showing that the system "dynamically" loads configuration data to reconfigure its hardware for different functions during active operation.