DCT

2:22-cv-00293

Netlist Inc v. Samsung Electronics Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:22-cv-00293, E.D. Tex., 07/20/2023
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants have committed acts of patent infringement in the district and maintain regular and established places of business in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s DDR3 and DDR4 server memory modules, including Load-Reduced and Registered DIMMs, infringe patents related to memory module architecture, specifically concerning rank multiplication and data buffering techniques.
  • Technical Context: The technology at issue involves high-performance computer memory modules used in servers and data-intensive applications, focusing on methods to increase memory capacity, improve signal integrity, and manage data flow between a memory controller and DRAM chips.
  • Key Procedural History: The complaint alleges that Plaintiff provided Defendant with notice of the asserted patents and their alleged infringement prior to the lawsuit. Specifically, Plaintiff alleges Defendant had knowledge of the ’912 patent family as early as 2010 through industry standards meetings and presentations, and received a licensing negotiation letter identifying the ’912 and ’215 patents no later than April 28, 2021. The complaint alleges Defendant had actual knowledge of the ’417 patent since no later than April 1, 2022. These allegations form the basis for claims of willful infringement.

Case Timeline

Date Event
2004-03-05 Earliest Priority Date for U.S. Patent No. 7,619,912
2004-05-28 Earliest Priority Date for U.S. Patent Nos. 11,093,417 and 9,858,215
2009-11-17 U.S. Patent No. 7,619,912 Issues
2010-01-01 Defendant allegedly gains knowledge of ’912 patent at JEDEC meeting
2015-01-01 Defendant allegedly gains knowledge of ’912 patent via presentation
2018-01-02 U.S. Patent No. 9,858,215 Issues
2021-04-28 Plaintiff sends licensing negotiation letter to Defendant for ’912 and ’215 patents
2021-08-17 U.S. Patent No. 11,093,417 Issues
2022-04-01 Defendant allegedly gains knowledge of ’417 patent
2023-07-20 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,619,912 - "Memory Module Decoder"

  • Patent Identification: U.S. Patent No. 7,619,912, "Memory Module Decoder," issued November 17, 2009.

The Invention Explained

  • Problem Addressed: The patent’s background section describes that conventional computer systems support a limited number of memory ranks, which in turn limits the total memory capacity that can be installed via memory modules (’912 Patent, col. 1:20-2:42).
  • The Patented Solution: The invention uses on-module logic to make a memory module with a large number of physical memory ranks appear to the computer system as a module with a smaller number of virtual ranks that the system can support (’912 Patent, col. 6:64-7:19). This technique, known as "rank multiplication," involves a logic element that receives a limited set of input control signals from the computer system and decodes them into a larger set of output signals to select from among the greater number of physical ranks (Compl. ¶25, ¶28). Figure 1A of the patent illustrates this concept, showing a logic element (40) receiving two chip-select signals but generating four internal chip-select signals to address four physical ranks of memory devices (’912 Patent, Fig. 1A).
  • Technical Importance: This approach allows for the creation of higher-capacity memory modules and enables the use of lower-density, and often more cost-effective, memory devices to achieve a desired module capacity (Compl. ¶26).

Key Claims at a Glance

  • The complaint asserts independent claim 16 of the ’912 patent (Compl. ¶39).
  • Essential elements of claim 16:
    • A memory module comprising a printed circuit board.
    • A plurality of memory devices on the board, arranged in a "first number of physical ranks."
    • A logic element on the board configured to receive input control signals corresponding to a "second number of virtual ranks," where the second number is smaller than the first number.
    • The logic element is further configured to generate output control signals corresponding to the first number of physical ranks in response to the input signals.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 11,093,417 - "Memory Module With Data Buffering"

  • Patent Identification: U.S. Patent No. 11,093,417, "Memory Module With Data Buffering," issued August 17, 2021.

The Invention Explained

  • Problem Addressed: While not explicitly stated as a problem, the patent specification describes an architecture for managing high-speed data transfers on memory modules that use data buffers, a design required to maintain signal integrity as memory densities and speeds increase on server-class modules (’417 Patent, col. 1:45-2:4).
  • The Patented Solution: The invention is a memory module architecture where on-module "logic" (such as a Registering Clock Driver, or RCD) receives memory commands and, in response, issues not only registered address and control signals to the memory devices but also separate "data buffer control signals" to buffering "circuitry" positioned between the main memory bus and the DRAM chips (’417 Patent, Abstract). These signals enable "registered transfers" of data through the buffers. A central element of the solution is that this buffering introduces a delay, such that the "overall CAS latency of the memory module" as seen by the system controller is "greater than an actual operational CAS latency of the memory devices" themselves (Compl. ¶31).
  • Technical Importance: This buffered architecture is a key enabling technology for Load-Reduced DIMMs (LRDIMMs), which allow servers to support significantly higher memory capacities than is possible with traditional Registered DIMMs (RDIMMs) (Compl. ¶16, ¶20).

Key Claims at a Glance

  • The complaint asserts independent claim 1 of the ’417 patent (Compl. ¶44).
  • Essential elements of claim 1:
    • A memory module operable to communicate data with a memory controller via an N-bit wide memory bus.
    • Memory devices mounted on a printed circuit board and arranged in N-bit wide ranks.
    • Logic configurable to receive input address and control signals for a memory command and to output registered address/control signals and "data buffer control signals."
    • Circuitry coupled between the memory bus and the memory devices.
    • The circuitry is configurable to enable "registered transfers" of N-bit wide data signals in response to the data buffer control signals.
    • These transfers occur in accordance with an "overall CAS latency" for the module that is greater than the "actual operational CAS latency" of the memory devices.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

Multi-Patent Capsule

  • Patent Identification: U.S. Patent No. 9,858,215, "Memory Module With Data Buffering," issued January 2, 2018.
  • Technology Synopsis: This patent relates to a memory module with a buffer and logic for managing data transfers. The invention focuses on the logic providing a first set of control signals to the buffer in response to a first memory command (e.g., a read) to manage a first data burst, and a second set of control signals in response to a second memory command (e.g., a write) to manage a second data burst (Compl. ¶34; ’215 Patent, Abstract). This addresses the need to issue distinct instructions to the data buffer depending on the specific operation being performed.
  • Asserted Claims: Claim 1 (Compl. ¶58).
  • Accused Features: The complaint accuses Micron's DDR4 LRDIMMs, alleging their logic (RCD) provides different control signals to their data buffers to manage data bursts for different memory commands, such as a read versus a write command. The complaint provides an annotated timing diagram illustrating a first memory command (Read) followed by a second memory command (Write) to exemplify this operation (Compl. ¶60, p. 35).

III. The Accused Instrumentality

Product Identification

The "Accused Products" are identified as any Micron DDR3 and DDR4 LRDIMM (Load-Reduced Dual In-line Memory Module) and RDIMM (Registered Dual In-line Memory Module) products (Compl. ¶37). For the ’912 patent, the accused products are specified as those that employ "per DRAM addressability ('PDA')" (Compl. ¶37).

Functionality and Market Context

The accused products are high-performance memory modules intended for use in servers and other data-intensive applications like cloud computing and high-performance computing (Compl. ¶18, ¶35). The complaint alleges that LRDIMMs, in particular, function using a distributed buffer architecture that includes a Registering Clock Driver (RCD) and data buffers (Compl. ¶20, ¶47, ¶51). The complaint provides a product description from Micron's website for a "DDR4 SDRAM LRDIMM Core" product, which is described as being "intended for use as main memory when installed in servers" (Compl. ¶45, p. 14). Functionally, the RCD receives command and address signals and re-drives them to the DRAM chips, while data buffers manage the flow of data between the memory controller and the DRAMs, reducing the electrical load on the memory bus (Compl. ¶20, ¶47-49).

IV. Analysis of Infringement Allegations

7,619,912 Patent Infringement Allegations

The complaint alleges that Micron’s DDR4 LRDIMM and RDIMM products that employ "per DRAM addressability ('PDA')" infringe at least claim 16 of the ’912 Patent (Compl. ¶37, ¶39). The complaint states that an exemplary claim chart is attached as Exhibit 4 but does not provide the exhibit or a detailed narrative of the infringement theory in the body of the complaint (Compl. ¶39). The core theory of infringement appears to be that Micron's "PDA" feature constitutes the "logic element" required by claim 16 and performs the claimed function of "rank multiplication" by receiving control signals corresponding to a certain number of virtual ranks and generating control signals corresponding to a larger number of physical ranks (Compl. ¶25, ¶37).

11,093,417 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A memory module operable...to communicate data with a memory controller...via a N-bit wide memory bus... Accused DDR4 LRDIMMs are memory modules that communicate with a memory controller via a data bus with address, control, and data signal lines. A schematic shows the memory bus includes address ("Ax"), control ("CSx_n"), and data ("DQx") lines. ¶45, ¶46 col. 2:54-61
memory devices mounted on a printed circuit board and arranged in a plurality of N-bit wide ranks; Accused DDR4 LRDIMMs comprise a printed circuit board ("PCB") with SDRAM memory devices mounted on it. A functional block diagram shows memory devices (e.g., U1-U38) arranged in ranks (Rank 0, Rank 1). ¶47, ¶50 col. 3:55-58
logic...configurable to receive a set of input address and control signals...and to output registered address and control signals and data buffer control signals; Accused DDR4 LRDIMMs include logic (an RCD) that receives input chip select signals and outputs registered chip selects. JEDEC standards show the logic outputs data buffer control signals (e.g., BCOM[3:0]=1001 for read) via a data buffer control bus. ¶48, ¶49 col. 3:58-65
circuitry...configurable to enable registered transfers of...data signals...in response to the data buffer control signals and in accordance with an overall CAS latency...which is greater than an actual operational CAS latency of the memory devices. The circuitry (DDR4 data buffers) is configurable to transfer data bursts in response to the data buffer control signals (e.g., BCOM[3:0]). JEDEC standards provide equations showing the overall module latency is a sum of multiple components, including the DRAM's CAS latency (CL), resulting in an overall latency greater than the DRAM's actual operational latency. ¶51, ¶52, ¶53 col. 4:1-12

Identified Points of Contention

  • Scope Questions: A potential issue may be the construction of "logic" and "circuitry." The complaint alleges the RCD is the "logic" and the data buffers are the "circuitry." A defendant might argue that the claimed functions are performed by a single, integrated component or in a manner different from the patent's description, raising questions about whether the accused product's architecture maps to the distinct elements required by the claim.
  • Technical Questions: The infringement case for the ’417 patent will likely depend on detailed technical evidence from JEDEC standards and Micron datasheets. A central question will be whether the complaint's interpretation of these documents accurately reflects the operational reality of the accused LRDIMMs, specifically regarding the calculation of "overall CAS latency" and proving it is functionally greater than the "actual operational CAS latency" of the DRAM chips in the manner claimed.

V. Key Claim Terms for Construction

For U.S. Patent No. 7,619,912

  • The Term: "logic element"
  • Context and Importance: This term is the central component performing the invention. Its construction will determine whether the on-module component in the Accused Products—alleged to be related to Micron's "PDA" feature—meets this claim limitation. Practitioners may focus on this term because the complaint's theory hinges on equating "PDA" with the claimed "logic element."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claims define the term functionally: "configured to receive a set of input control signals...and...to generate a set of output control signals" (’912 Patent, cl. 16). The specification describes it as a "decoder" and states it can be implemented in various ways, including with a "programmable logic device (PLD)" (’912 Patent, col. 6:50-51), which may support a broad, functional definition.
    • Evidence for a Narrower Interpretation: The patent's primary embodiment, Figure 1A, depicts the "logic element (40)" as a distinct and separate component from the "register (60)" (’912 Patent, Fig. 1A). A defendant might argue this suggests the term does not read on a standard registering component (like an RCD) but requires a separate, dedicated decoding circuit.

For U.S. Patent No. 11,093,417

  • The Term: "overall CAS latency of the memory module, which is greater than an actual operational CAS latency of the memory devices"
  • Context and Importance: This limitation defines the functional outcome of the claimed buffering architecture. Proving infringement requires demonstrating not just the presence of buffers, but that they operate to create this specific latency relationship. Practitioners may focus on this term because it links the structural elements of the claim (logic, circuitry) to a required functional result.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent's abstract frames this as a key feature of the invention, linking it directly to the "registered transfers" enabled by the buffering circuitry (’417 Patent, Abstract). This suggests that any buffering architecture that necessarily introduces a delay between the controller and the DRAMs, thereby increasing the total latency, could fall within the claim's scope.
    • Evidence for a Narrower Interpretation: The detailed description does not provide a specific formula but describes the concept in the context of the overall buffered system (’417 Patent, col. 4:1-12). A defendant could argue that this phrase is indefinite or that it implies a specific type of "registered transfer" or buffering scheme detailed in the specification, potentially limiting the claim's scope to exclude standard LRDIMM operations.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all three patents-in-suit. Inducement is alleged based on Defendant providing "specifications, datasheets, instruction manuals, and/or other materials that encourage and facilitate infringing use" by its customers and end-users (Compl. ¶40, ¶54, ¶67).
  • Willful Infringement: Willfulness is alleged for all three patents based on alleged pre-suit knowledge. For the ’912 and ’215 patents, knowledge is alleged as early as 2010 from a JEDEC standards meeting, a 2015 presentation to Micron, and a licensing letter dated April 28, 2021 (Compl. ¶42, ¶69). For the ’417 patent, knowledge of predecessor patents is alleged for the same periods, with knowledge of the ’417 patent itself alleged since at least April 1, 2022 (Compl. ¶56). The complaint asserts Defendant's infringement has been continuous and willful despite a high likelihood its actions constitute infringement (Compl. ¶42, ¶56, ¶69).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of technical and semantic equivalence: Does Micron's "Per DRAM Addressability" (PDA) feature, as implemented in its RDIMM and LRDIMM products, perform the function of the "logic element" claimed in the ’912 patent? The case may turn on whether "PDA" is simply a trade name for the claimed "rank multiplication" or a distinct, non-infringing technology.
  • A second central issue will be the interpretation of industry standards: For the ’417 and ’215 patents, the dispute will likely focus on whether the operation of a JEDEC-compliant LRDIMM inherently practices the claimed inventions. This raises the evidentiary question of whether the functions described in JEDEC technical documents for LRDIMMs—such as managing data flow through buffers and accounting for added latency—map directly onto the specific limitations recited in the asserted claims.
  • Finally, the case presents a significant question regarding damages and willfulness: Given the allegations of knowledge dating back over a decade for the underlying technology, a key battleground, should infringement be found, will be the extent of Defendant's alleged willfulness and the appropriate measure of damages for foundational memory technologies that have been widely adopted through industry standards.