Netlist Inc v. Micron Technology Texas LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Netlist, Inc. (Delaware)
  • Defendant: Micron Technology, Inc. (Delaware); Micron Semiconductor Products, Inc. (Idaho); Micron Technology Texas LLC (Idaho)
  • Plaintiff’s Counsel: McKOOL SMITH, P.C.; Irell & Manella LLP
• Case Identification: 2:22-cv-00294, E.D. Tex., 08/15/2022
• Venue Allegations: Plaintiff alleges venue is proper because Defendants commit acts of patent infringement in the district and maintain regular and established places of business within the district.
• Core Dispute: Plaintiff alleges that Defendant’s DDR4 LRDIMM and RDIMM memory products infringe three patents related to high-performance memory module architecture, including technologies for rank multiplication and data buffering.
• Technical Context: High-performance memory modules are essential components in data-intensive computing systems such as servers, where maximizing memory capacity and speed is critical for performance.
• Key Procedural History: The complaint alleges that Plaintiff notified Defendant Micron of U.S. Patent Nos. 7,619,912 and 9,858,215 and requested that it take a license by letter dated April 28, 2021, which Defendant declined. This allegation may form the basis for a claim of pre-suit willful infringement for those two patents.

Case Timeline

Date	Event
2004-05-28	Earliest Priority Date for ’912, ’417, and ’215 Patents
2009-11-17	U.S. Patent No. 7,619,912 Issues
2018-01-02	U.S. Patent No. 9,858,215 Issues
2021-04-28	Plaintiff allegedly sends letter to Defendant requesting license
2021-08-17	U.S. Patent No. 11,093,417 Issues
2022-08-15	First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,619,912 - "Memory Module Decoder"

Issued November 17, 2009

The Invention Explained

• Problem Addressed: The patent’s background section, as paraphrased in the complaint, describes a fundamental limitation in computer systems at the time of the invention: they could typically only support a small number of memory "ranks" per memory slot, which constrained the total memory capacity that could be installed (Compl. ¶24; ’912 Patent, col. 1:20-2:42).
• The Patented Solution: The invention uses on-module logic to make a memory module with a larger number of physical ranks of memory devices appear to the host computer system as if it has a smaller number of "virtual" ranks. This technique, known as "rank multiplication," allows a module with, for example, four physical ranks to be controlled by a system that only supports two ranks (Compl. ¶25; ’912 Patent, col. 6:64-7:19). Figure 1A of the patent illustrates a logic element that receives two chip-select signals from the system and generates four corresponding chip-select signals for the internal memory devices (Compl. ¶27-28).
• Technical Importance: This approach allowed designers to increase a memory module's total capacity beyond what the host system was designed to support and enabled the use of lower-density, and often less expensive, memory chips to construct high-capacity modules (Compl. ¶26).

Key Claims at a Glance

• The complaint asserts independent claim 16 (Compl. ¶39).
• The essential elements of claim 16 are:
  • A memory module connectable to a computer system.
  • A printed circuit board.
  • A plurality of double-data-rate (DDR) memory devices coupled to the board and arranged in a first number of ranks.
  • A circuit comprising a logic element and a register, which receives a set of input control signals from the computer system.
  • The input control signals correspond to a second number of ranks, which is smaller than the first number of ranks.
  • The circuit generates a set of output control signals corresponding to the first number of ranks.
  • The circuit responds to a first command signal from the system by generating and transmitting a second command signal to the memory devices.
  • A phase-lock loop device coupled to the memory devices, logic element, and register.
• The complaint reserves the right to assert additional claims (Compl. ¶39, fn. 1).

U.S. Patent No. 11,093,417 - "Memory Module With Data Buffering"

Issued August 17, 2021

The Invention Explained

• Problem Addressed: As memory module capacities increase, more memory devices are placed on a single printed circuit board, which can degrade signal integrity and performance. The patent background notes the need to improve the performance and memory capacity of memory modules (’417 Patent, col. 2:2-4).
• The Patented Solution: The invention describes a memory module architecture that includes logic and buffering circuitry placed between the system's memory bus and the memory devices. This circuitry enables "registered transfers" of data, which are managed by "data buffer control signals." A key aspect of the solution is that this buffering introduces a time delay, such that the "overall CAS latency of the memory module...is greater than an actual operational CAS latency of the memory devices" (Compl. ¶31; ’417 Patent, Abstract). This architecture effectively isolates the electrical load of the memory devices from the host controller, improving signal integrity.
• Technical Importance: This buffered architecture is foundational to modern high-capacity, high-speed memory modules like Load-Reduced DIMMs (LRDIMMs), allowing servers to support larger amounts of memory than would be possible with traditional unbuffered designs.

Key Claims at a Glance

• The complaint asserts independent claim 1 (Compl. ¶41).
• The essential elements of claim 1 are:
  • A memory module operable in a computer system to communicate data with a memory controller via an N-bit wide memory bus.
  • Logic coupled to the printed circuit board, configurable to receive input address and control signals and to output registered address and control signals and data buffer control signals.
  • Memory devices mounted on the printed circuit board and arranged in a plurality of N-bit wide ranks.
  • Circuitry coupled between the memory bus and the memory devices, configurable to transfer a burst of N-bit wide data signals in response to the data buffer control signals and in accordance with an overall CAS latency of the memory module that is greater than an actual operational CAS latency of each of the memory devices.
• The complaint reserves the right to assert additional claims (Compl. ¶41, fn. 1).

U.S. Patent No. 9,858,215 - "Memory Module With Data Buffering"

Issued January 2, 2018

Technology Synopsis

The patent relates to a memory module with a buffer and logic that manages data transfers between a memory controller and memory integrated circuits arranged in different ranks. The logic provides distinct control signals to the buffer to enable a first data burst for a first memory command and second, different control signals for a second data burst in response to a second memory command, allowing for communication with different memory ranks through the buffer (Compl. ¶34; ’215 Patent, Abstract).

Asserted Claims

The complaint asserts independent claim 1 (Compl. ¶55).

Accused Features

The complaint alleges that Defendants' DDR4 LRDIMMs, which contain a buffer and logic for communicating with multiple ranks of memory circuits, infringe the patent (Compl. ¶55-63). An annotated timing diagram in the complaint illustrates a first memory command (Read) followed by a second memory command (Write) (Compl. ¶57, p. 34).

III. The Accused Instrumentality

Product Identification

The accused products are Micron's DDR4 LRDIMM (Load-Reduced Dual In-line Memory Module) and RDIMM (Registered Dual In-line Memory Module) products (Compl. ¶37).

Functionality and Market Context

The accused products are high-performance memory modules intended for use in servers and other data-intensive applications (Compl. ¶42, Exhibit 6). The complaint alleges they comprise a printed circuit board, a plurality of memory devices (SDRAMs) arranged in ranks, and logic in the form of a Registering Clock Driver (RCD) (Compl. ¶44, 47). An included datasheet diagram shows the RCD (labeled U16) receiving address and control signals from the system and outputting signals to data buffers and DDR4 SDRAMs arranged in multiple ranks (Compl. ¶43, p. 15). The complaint alleges these products are sold for use in cloud computing and high-performance computing markets (Compl. ¶15, 35).

IV. Analysis of Infringement Allegations

The complaint does not provide sufficient detail for a claim chart analysis of the ’912 patent's infringement allegations. It states that an exemplary claim chart is attached as Exhibit 4, but this exhibit was not included with the filed complaint (Compl. ¶39). The narrative allegations are limited to a general assertion that accused products employing "per DRAM addressability ('PDA')" infringe claim 16 (Compl. ¶37).

’417 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a memory module operable in a computer system to communicate data with a memory controller of the computer system via a N-bit wide data bus in response to memory commands (e.g., read or write) received from the memory controller	The accused DDR4 LRDIMMs are memory modules designed for servers, operable to communicate data with a memory controller via a data bus in response to read or write commands. A product description for the accused products confirms this functionality (Compl. ¶42, p. 13).	¶42	col. 3:17-23
logic coupled to the printed circuit board and configurable to receive a set of input address and control signals... and to output a set of registered address and control signals... and data buffer control signals	The accused DDR4 LRDIMMs include logic (a DDR4 RCD) on a PCB that receives input address and control signals (e.g., Ax, CSx_n) and outputs registered signals. This logic is also configurable to output data buffer control signals (e.g., BCOM[3:0]) in response to a read or write command.	¶44-46	col. 3:29-43
memory devices mounted on the printed circuit board and arranged in a plurality of N-bit wide ranks, which correspond to respective ones of the plurality of registered chip select signals	The accused DDR4 LRDIMMs have memory devices (SDRAMs) on the PCB arranged in multiple N-bit wide ranks that receive registered chip select signals from the RCD. A functional block diagram from a product datasheet illustrates this arrangement (Compl. ¶47, p. 19).	¶47	col. 3:53-61
circuitry coupled between the data signal lines in the N-bit wide memory bus and corresponding data pins of memory devices... the circuitry being configurable to transfer the burst of N-bit wide data signals between the N-bit wide memory bus and the memory devices in the one of the plurality of N-bit wide ranks in response to the data buffer control signals and in accordance with an overall CAS latency of the memory module, which is greater than an actual operational CAS latency of each of the memory devices	The accused DDR4 LRDIMMs include circuitry (DDR4 data buffers) between the memory bus and the memory devices. This circuitry transfers data bursts in response to data buffer control signals (BCOM[3:0] codes). The data transfer through this circuitry adds a time delay, making the module's overall CAS latency greater than the operational CAS latency of the memory devices themselves.	¶48-50	col. 3:62-4:10

Identified Points of Contention

• Scope Questions: A central question for the '912 patent will be whether Micron's "per DRAM addressability" (PDA) technology falls within the scope of the patent's claims for "rank multiplication," which require a logic element that generates a larger set of output rank-select signals from a smaller set of input rank-select signals. For the '417 patent, a question may arise as to whether the standard RCD and data buffers in an LRDIMM constitute the claimed "logic" and "circuitry" performing the specific claimed functions.
• Technical Questions: For the '417 patent, a key technical question will be what evidence demonstrates that the accused products' "overall CAS latency" is in fact "greater than an actual operational CAS latency" of the memory devices. While the complaint provides standardized equations, the actual operation in a system will be a matter of proof.

V. Key Claim Terms for Construction

For the ’912 Patent

• The Term: "logic element generating a set of output control signals... corresponding to the first number of ranks in response to the set of input control signals... corresponding to a second number of ranks"
• Context and Importance: This functional language defines the core "rank multiplication" concept. The outcome of the case for this patent may depend on whether Micron's accused "PDA" technology is construed as performing this specific 2-to-4 (or N-to-2N) decoding function. Practitioners may focus on this term because it is the central point of novelty.
• Intrinsic Evidence for a Broader Interpretation: The specification may describe the logic element in general terms as a "decoder" or "logic," which could be argued to cover a wide range of address mapping or decoding schemes (’912 Patent, col. 6:50-54).
• Evidence for a Narrower Interpretation: The primary embodiment shown in Figure 1A illustrates a specific implementation where two chip select signals (CS₀, CS₁) and an address signal (Aₙ₊₁) are used to generate four distinct rank-select signals (CS₀ₐ, CS₀₈, CS₁ₐ, CS₁₈) (’912 Patent, col. 7:35-53). A defendant could argue this specific decoding scheme limits the claim's scope.

For the ’417 Patent

• The Term: "overall CAS latency of the memory module, which is greater than an actual operational CAS latency of each of the memory devices"
• Context and Importance: This limitation appears to be the primary point of distinction over prior art and is heavily emphasized in the infringement allegations. The case will require a technical determination of how latency is measured and whether the accused products meet this "greater than" requirement due to the claimed buffering structure.
• Intrinsic Evidence for a Broader Interpretation: The patent abstract and summary state that the circuitry enables "registered transfers," which inherently adds delay. A plaintiff might argue that any architecture that uses registered buffering to add at least one clock cycle of delay meets this limitation (’417 Patent, col. 3:5-10).
• Evidence for a Narrower Interpretation: The complaint itself refers to specific JEDEC standard timing equations (e.g., DB_WL(R) and DB_RL(R)) to explain how the overall latency is calculated (Compl. ¶50, pp. 27-28). A defendant may argue that the term should be construed in light of these specific, well-defined industry standards for calculating latency in buffered modules.

VI. Other Allegations

• Indirect Infringement: The complaint alleges that Micron induces infringement and contributes to the infringement of the ’417 and ’215 patents. Inducement is alleged based on Micron providing "specifications, datasheets, instruction manuals, and/or other materials that encourage and facilitate infringing use." Contributory infringement is alleged on the basis that the accused products have "no substantial noninfringing use" and constitute a material part of the invention (Compl. ¶51-52, 64-65).
• Willful Infringement: Willfulness is alleged for all three patents. For the ’912 and ’215 patents, the allegation is based on alleged pre-suit knowledge stemming from the April 28, 2021 letter from Netlist to Micron (Compl. ¶23, 33, 66). For the ’417 patent, the allegation is based on knowledge "at least as of the filing of the First Amended Complaint" (Compl. ¶30, 53).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of technical equivalence: does Micron's "per DRAM addressability" (PDA) functionality, as implemented in its accused products, operate in the same way as the "rank multiplication" described and claimed in the ’912 patent, which requires generating a larger set of output rank-selection signals from a smaller set of input signals?
• A key evidentiary question will be one of functional proof: can Plaintiff demonstrate, through technical evidence, that the accused LRDIMMs' use of an RCD and data buffers necessarily results in an "overall CAS latency" that is provably "greater than an actual operational CAS latency" of the constituent memory devices, as required by the '417 patent claims?
• A central question of claim construction will be how to define and measure the respective "latencies" of the module and the devices for the '417 patent. The dispute may turn on whether the terms are given their plain meaning or are limited by the specific timing equations referenced in industry standards cited in the complaint.