DCT

2:22-cv-00353

Daedalus Prime LLC v. Samsung Electronics Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:22-cv-00353, E.D. Tex., 01/24/2023
  • Venue Allegations: Venue is alleged to be proper based on Defendants' personal jurisdiction in the district, acts of infringement in the district, and for Samsung Electronics America, Inc., a regular and established place of business in Plano, Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s semiconductor chips (including the Snapdragon and Exynos series SoCs) and the electronic devices that contain them (such as Galaxy smartphones) infringe six patents, originally invented by Intel, related to microprocessor power management, cache architecture, hardware security, and mobile device radio control.
  • Technical Context: The patents address fundamental challenges in modern semiconductor design, including managing power consumption in multi-core processors, optimizing data access in complex cache hierarchies, and securing mobile communications.
  • Key Procedural History: The complaint alleges that during the prosecution of its own separate patent applications, Samsung Electronics Co., Ltd. was made aware of patent applications that would eventually lead to the '135, '960, '197, and '838 patents-in-suit when they were cited as prior art by patent examiners.

Case Timeline

Date Event
2009-09-25 U.S. Patent No. 8,359,629 Priority Date
2011-06-30 U.S. Patent No. 9,432,840 Priority Date
2011-12-15 U.S. Patent No. 10,372,197 Priority Date
2011-12-15 U.S. Patent No. 9,887,838 Priority Date
2012-05-10 U.S. Patent No. 9,996,135 Priority Date
2012-12-28 U.S. Patent No. 10,705,960 Priority Date
2013-01-22 U.S. Patent No. 8,359,629 Issued
2016-08-30 U.S. Patent No. 9,432,840 Issued
2017-06-26 Examiner allegedly cites application leading to '135 Patent to Defendant SEC
2018-02-06 U.S. Patent No. 9,887,838 Issued
2019-08-06 U.S. Patent No. 10,372,197 Issued
2019-08-27 U.S. Patent No. 9,996,135 Issued
2020-07-07 U.S. Patent No. 10,705,960 Issued
2021-04-02 Examiner allegedly cites application related to '838 Patent to Defendant SEC
2023-01-24 Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,996,135 - Controlling Operating Voltage of a Processor (Issued Aug. 27, 2019)

The Invention Explained

  • Problem Addressed: The patent identifies that as the density of integrated circuits has grown, power requirements have escalated, and increased energy consumption has become a significant problem in computing devices ('135 Patent, col. 1:26-32).
  • The Patented Solution: The invention proposes a method for more efficiently managing voltage increases in a multi-core processor. When one core needs a higher voltage to operate at a higher frequency, the power controller first raises the voltage to an "interim" level. This interim voltage is sufficient to allow a second, inactive core to wake up. Only after the second core is enabled to become active is the voltage for the first core increased to its final, higher target level ('135 Patent, Abstract; Fig. 1). This sequencing aims to optimize the power-up process.
  • Technical Importance: This staged approach to voltage regulation allows for more granular power control in multi-core environments, potentially reducing latency when bringing additional cores online from inactive states ('135 Patent, col. 2:3-6).

Key Claims at a Glance

  • Independent Claim 1 is asserted (Compl. ¶62).
  • Essential elements of Claim 1:
    • A processor comprising a plurality of cores.
    • A power controller with control logic.
    • The logic is configured to:
      • receive a first request to increase an operating voltage for a first core to a second voltage.
      • responsive to the request, cause a voltage regulator to increase the operating voltage to an interim voltage.
      • thereafter enable a second core to exit an inactive state and enter an active state.
      • thereafter enable an operating frequency of the first core to be increased.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 10,705,960 - Processors Having Virtually Clustered Cores and Cache Slices (Issued July 7, 2020)

The Invention Explained

  • Problem Addressed: The patent notes that while multi-core processors increase throughput, they can suffer from longer latencies when accessing a shared cache and can "increase the memory address entropy at memory controllers," leading to lower effective memory bandwidth ('960 Patent, col. 1:32-47).
  • The Patented Solution: The invention describes a system of "virtually clustered" cores and cache slices. A multi-core processor is divided into logical clusters. When a core needs data not in its local cache, the request is first directed only to the cache slices within its own virtual cluster ('960 Patent, Abstract). The system also uses different operating frequencies for different clusters and can selectively power gate clusters to manage power ('960 Patent, col. 9:44-10:4). This architecture aims to reduce latency and increase memory bandwidth by localizing data access patterns.
  • Technical Importance: Virtual clustering provides a method to manage the communication and power overhead in processors with a large number of cores, attempting to gain the benefits of a large shared cache while mitigating the performance penalties of non-uniform access times ('960 Patent, col. 1:48-54).

Key Claims at a Glance

  • Independent Claim 1 is asserted (Compl. ¶85).
  • Essential elements of Claim 1:
    • A system with a plurality of symmetric multi-threaded cores.
    • A cache subsystem with first-level caches and a higher-level distributed cache (with distributed portions shared by the cores).
    • Cache management circuitry for coherent, non-uniform access.
    • Power management circuitry to enable a first frequency for a first cluster of physically proximate cores and a second frequency for a second cluster of physically proximate cores, where the average distance between cores in the first cluster is less than the average distance between all cores.
    • The power management circuitry is also operative to selectively gate power to the clusters and their corresponding distributed cache portions.
    • A first and a second integrated memory controller coupled with the cores.
  • The complaint does not explicitly reserve the right to assert dependent claims.

Multi-Patent Capsule: U.S. Patent No. 10,372,197

  • Patent Identification: U.S. Patent No. 10,372,197, "User Level Control of Power Management Policies," Issued Aug. 6, 2019.
  • Technology Synopsis: The patent describes a processor with a power controller that receives user-level or OS-level input about the current workload and an "energy performance bias" (EPB) value. It uses this input to consult a tuning table and dynamically update power management settings, allowing a user to express a preference for performance versus power savings ('197 Patent, Abstract; col. 2:35-40).
  • Asserted Claims: Claim 1 is asserted (Compl. ¶121).
  • Accused Features: The accused feature is ARM's Intelligent Power Allocation technology, allegedly used in conjunction with Power Policy Units in the Snapdragon 888 and Exynos 2200 SoCs to receive workload configuration input and EPB values to update power settings (Compl. ¶¶132-135). A diagram from an ARM whitepaper is provided to illustrate the accused functionality (Compl. ¶135, p. 45).

Multi-Patent Capsule: U.S. Patent No. 9,887,838

  • Patent Identification: U.S. Patent No. 9,887,838, "Method And Device For Secure Communications Over A Network Using A Hardware Security Engine," Issued Feb. 6, 2018.
  • Technology Synopsis: The patent claims a system-on-a-chip (SoC) with a dedicated security engine that is separate from the main processor core. This engine has its own secure memory, containing a security key encoded during manufacturing, and is used to generate nonces, perform key exchanges, and store session keys to establish a secure communication session with a remote server ('838 Patent, Abstract).
  • Asserted Claims: Claim 1 is asserted (Compl. ¶151).
  • Accused Features: The complaint alleges that Samsung's Knox security platform, which implements ARM TrustZone, infringes. It is alleged that ARM TrustZone creates a "Secure World" that functions as a security engine separate from the processor core's "Normal World" and uses a device key generated at manufacture to secure communications (Compl. ¶¶153-154).

Multi-Patent Capsule: U.S. Patent No. 8,359,629

  • Patent Identification: U.S. Patent No. 8,359,629, "Method and Device for Controlling Use of Context Information of a User," Issued Jan. 22, 2013.
  • Technology Synopsis: The patent describes a method for a mobile device to control the sharing of a user's context information (e.g., location). A "context policy enforcement engine" on the device receives a request for information and consults a set of rules to determine what level of specificity to provide (e.g., exact coordinates vs. just the city name) based on the identity of the requesting entity ('629 Patent, Abstract).
  • Asserted Claims: Claim 1 (a method claim) and Claim 21 (likely a product claim) are asserted (Compl. ¶¶46, 179).
  • Accused Features: The accused products are Samsung Galaxy smartphones and tablets that allegedly employ a "Samsung Android Context Policy." The Android OS is alleged to act as the context policy enforcement engine, using user-defined location tracking settings (the "rules") to determine the level of location specificity provided to requesting apps (Compl. ¶¶179, 183, 185).

Multi-Patent Capsule: U.S. Patent No. 9,432,840

  • Patent Identification: U.S. Patent No. 9,432,840, "Radio Based Location Power Profiles," Issued Aug. 30, 2016.
  • Technology Synopsis: The patent addresses battery life in mobile devices by automatically managing radios like Wi-Fi. The device uses location profiles, where each profile is associated with a location and includes criteria for entering/exiting that location and settings for which radios to activate or deactivate. When a location change is detected, the device activates the Wi-Fi radio based on the relevant profile ('840 Patent, Abstract).
  • Asserted Claims: Claim 6 is asserted (Compl. ¶198).
  • Accused Features: The complaint accuses Samsung's "Intelligent Wi-Fi" and/or "Adaptive Wi-Fi" features, available on devices like the Samsung Galaxy S10. This feature is alleged to use location profiles ("favorite networks") and geofencing to detect location changes and automatically turn the Wi-Fi radio on or off (Compl. ¶¶204, 206).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are primarily System-on-a-Chip (SoC) processors and the consumer electronic devices containing them (Compl. ¶¶57-59). Specific SoCs identified include the Qualcomm Snapdragon 888, Snapdragon 835, and Samsung Exynos 2200, which are based on ARMv8.2 or ARMv9 architecture (Compl. ¶¶58, 62). Specific consumer devices include the Samsung Galaxy S-series and Note-series smartphones and Samsung Galaxy tablets (Compl. ¶¶58-59).

Functionality and Market Context

  • The complaint alleges these SoCs contain multi-core processors with sophisticated power management and security features (Compl. ¶58). For the '135 and '960 patents, the key functionalities are the power management logic, such as ARM Power Policy Units, and the multi-core cache architecture, such as the DynamIQ Shared Unit (DSU) (Compl. ¶¶68, 94).
  • The smartphones and tablets are alleged to incorporate features like "Intelligent Wi-Fi" for radio management and variable-resolution location sharing for context privacy, which are accused of infringing the '840 and '629 patents, respectively (Compl. ¶59). The Samsung Knox security platform is accused of infringing the '838 patent (Compl. ¶154).
  • The complaint positions Samsung as a global leader in semiconductor manufacturing and a major manufacturer of electronic components, highlighting the commercial significance of the accused products (Compl. ¶56).

IV. Analysis of Infringement Allegations

'135 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A processor comprising: a plurality of cores; The Snapdragon 888 and Exynos 2200 SoCs contain multiple processor cores, such as ARM Cortex-X1, A78, and A55 cores. A diagram of the Snapdragon 888 architecture shows these distinct core clusters (Compl. ¶65, p. 22). ¶63-65 col. 2:56-58
and a power controller including a control logic to receive a first request to increase an operating voltage to be provided to a first core to a second voltage and, responsive to the first request, cause a voltage regulator to increase the operating voltage to an interim voltage, thereafter enable a second core to exit an inactive state and enter an active state, and thereafter enable an operating frequency of the first core to be increased. The accused SoCs allegedly include ARM Power Policy Units (PPUs) or similar logic that manage power for CPU cores. This logic is alleged to receive a request (e.g., from a System Control Processor) to increase voltage, and then automatically perform the necessary transitions to reach the requested power mode, which is alleged to include the claimed sequence of increasing to an interim voltage before waking a second core and then increasing the first core's frequency. ¶67-69 col. 4:1-13
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the operations performed by the accused ARM Power Policy Units constitute the specific, ordered sequence of steps required by the claim. The claim requires increasing to an "interim voltage," then enabling a second core, and then enabling the frequency increase of the first core.
    • Technical Questions: What evidence does the complaint provide that the accused power transitions are not merely a voltage ramp to the final target, but involve a distinct "interim voltage" step whose purpose is tied to the wakeup of a second core, as the claim structure suggests? The complaint alleges the PPU "automatically makes the necessary transitions" but does not detail what those specific transitions are or their sequence (Compl. ¶69).

'960 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a plurality of cores, the plurality of cores comprising symmetric multi-threaded cores; Accused SoCs include two or more identical ARM processor cores (e.g., multiple Cortex-A78 cores in the Snapdragon 888) that are alleged to be symmetric and support multithreading in conjunction with the Android OS. Documentation from ARM and Android is cited to show support for multithreading (Compl. ¶¶ 89-90, p. 29-30). ¶87-90 col. 2:1-3
a cache subsystem... comprising a plurality of first level caches and at least one higher level distributed cache comprising a plurality of distributed cache portions that are physically distributed across a die and shared by the plurality of cores... The Exynos 2200 and Snapdragon 888 SoCs are alleged to include L1, L2, and L3 caches. The L3 caches are described as being physically distributed across the die and shared by the cores, with L1/L2 caches integral to specific cores. ¶91-92 col. 2:4-14
cache management circuitry operative to provide coherent, non-uniform access to the plurality of distributed cache portions... The accused SoCs allegedly include a DynamIQ Shared Unit (DSU), which comprises the cache management circuitry that provides coherent, non-uniform access to the distributed L3 cache portions. ¶93-95 col. 2:15-18
power management circuitry operative to enable a first frequency of operation for a first cluster of the plurality of cores which are physically proximate...and a second frequency... The DSU in the accused SoCs allegedly includes Power Policy Units (PPUs) and a Power Control Module that provide Dynamic Voltage and Frequency Scaling (DVFS) control on a per-core and per-cluster level. ¶96-98 col. 2:19-32
...operative to selectively gate power the first cluster...and distributed cache portions... The PPUs in the accused Exynos SoCs are alleged to provide power management features including selectively reducing power to individual CPU cluster cores and powering down L3 cache slices. A technical diagram shows pin-controlled reset domains for the DSU, including for cores and L3 RAM arrays (Compl. ¶102, p. 34). ¶101-103 col. 2:33-42
a first integrated memory controller coupled with the symmetric multi-threaded cores; and a second integrated memory controller... The Samsung Exynos 2200 and Snapdragon 888 SoCs are alleged to comprise at least two separate channels of LPDDR5 memory control, which constitute at least two integrated memory controllers. ¶105 col. 2:43-47
  • Identified Points of Contention:
    • Scope Questions: Does the architecture of the accused SoCs, such as ARM's big.LITTLE, meet the claim requirement of "symmetric multi-threaded cores"? The complaint alleges symmetry based on clusters of identical cores (e.g., multiple Cortex-A78s), but the overall SoC often combines different types of cores (e.g., Cortex-X1 and Cortex-A55) (Compl. ¶¶65, 88). The definition of "symmetric" will be critical.
    • Technical Questions: Does the accused "DynamIQ Shared Unit" perform the claimed function of enabling different frequencies for different "clusters of physically proximate cores" where proximity is defined by the average-distance limitation in the claim? The infringement allegation will depend on the physical layout of the cores on the die and how the DVFS is implemented across those layouts.

V. Key Claim Terms for Construction

For the '135 Patent

  • The Term: "interim voltage"
  • Context and Importance: This term is central to the claimed invention's novelty, which lies in a specific sequence of power-up events. The definition of "interim voltage" will determine whether any voltage increase during a ramp-up qualifies, or if it must be a distinct, stable voltage level maintained for a specific purpose (i.e., enabling a second core to wake up) before a subsequent increase.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification does not appear to provide an explicit definition of "interim voltage," which may support an argument that it should be given its plain and ordinary meaning, potentially covering any voltage level between the starting and final voltages in a ramp.
    • Evidence for a Narrower Interpretation: The claim structure itself implies a function: the voltage is increased to an interim level, and thereafter a second core is enabled. This suggests the "interim voltage" is a specific level sufficient to achieve that function. The patent states the goal is to reduce latency for a low power state exit, which is achieved by this sequencing, implying the interim voltage is a discrete step in that ordered process ('135 Patent, col. 2:3-6).

For the '960 Patent

  • The Term: "symmetric multi-threaded cores"
  • Context and Importance: Practitioners may focus on this term because the accused products utilize ARM's big.LITTLE architecture, which famously combines different types of cores (e.g., high-performance "big" cores and high-efficiency "LITTLE" cores) in a single SoC. Whether a processor containing different types of cores can still meet the "symmetric" limitation will be a core dispute.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification does not provide a specific definition for "symmetric." A party could argue that if the processor contains a plurality of cores that are themselves symmetric (e.g., a cluster of four identical Cortex-A78 cores), the limitation is met, even if other, different cores also exist on the same die.
    • Evidence for a Narrower Interpretation: A defendant may argue that "symmetric" applies to the "plurality of cores" as a whole, meaning all or substantially all cores in the processor must be identical. The patent's figures, such as Figure 2, depict cores that are architecturally identical in the drawing, which could be used to argue the inventors contemplated a homogenous core environment ('960 Patent, Fig. 2).

VI. Other Allegations

  • Indirect Infringement: For all asserted patents, the complaint alleges induced infringement. The allegations are based on Samsung supplying the accused products to consumers and providing instructions (e.g., user manuals and technical documentation) that allegedly encourage use in an infringing manner (Compl. ¶¶73, 109). Contributory infringement is also alleged, based on Samsung providing components (e.g., the SoCs) that are a material part of the invention and are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶¶75, 111).
  • Willful Infringement: Willfulness is alleged for all asserted patents. The basis is two-fold: (1) alleged pre-suit knowledge based on Samsung's significant market position and alleged monitoring of Intel's patent activity, and more specifically, on patent office actions where applications leading to the patents-in-suit were cited against Samsung's own patent applications (Compl. ¶¶71, 107, 137, 165); and (2) post-suit knowledge based on the filing of the original complaint in the action (Compl. ¶¶80, 116, 146, 174).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of technical sequencing and operation: For the '135 patent, does the accused power management logic perform the precise three-step sequence of "increase to interim voltage," "enable second core," and "increase first core frequency," or is this an attempt to read limitations onto a more generalized voltage ramp?
  • A key question will be one of definitional scope: For the '960 patent, can the term "symmetric...cores" be construed to read on heterogeneous processor architectures like ARM's big.LITTLE, which combine different types of cores on a single die? The outcome may depend on whether "symmetric" is interpreted to require homogeneity across all cores or merely the presence of some symmetric clusters.
  • An evidentiary question will be one of pre-suit knowledge: Can Plaintiff demonstrate that Samsung's awareness of the patent applications (cited during unrelated patent prosecution) created an "unjustifiably high risk" of infringement of the subsequently issued patents, sufficient to support a finding of pre-suit willfulness, or will knowledge be limited to the date the complaint was filed?