Cedar Lane Tech Inc v. Luminator Technology Group Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: Luminator Technology Group, Inc. (Delaware)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:22-cv-00397, E.D. Tex., 10/11/2022
• Venue Allegations: Venue is alleged to be proper because Defendant has an established place of business in the district and has committed alleged acts of infringement causing harm in the district.
• Core Dispute: Plaintiff alleges that Defendant’s unspecified products infringe three patents related to interfacing image sensors with data compression and processing systems.
• Technical Context: The technology concerns methods for efficiently managing the flow of data from an image sensor (like those in digital cameras or scanners) to other components like processors or compression chips.
• Key Procedural History: The complaint does not mention any prior litigation, inter partes review proceedings, or licensing history related to the patents-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," Issued October 29, 2002

The Invention Explained

• Problem Addressed: The patent describes a problem in prior art image processing systems where an extra, external memory device was required to buffer data between an analog-to-digital (A/D) converter and a dedicated JPEG compression chip. This extra component added cost and inefficiency to devices like scanners. (’527 Patent, col. 1:49-57).
• The Patented Solution: The invention proposes an interface module that eliminates the need for the extra external memory. This module contains its own memory device sized to match the internal buffer of the JPEG compression chip (e.g., storing 8 lines of image data for an 8x8 pixel compression block). The module reads a set number of lines from the A/D converter, stores them, and then forwards formatted image blocks directly to the compression chip as needed, streamlining the data flow. (’527 Patent, Abstract; col. 2:49-57; Fig. 2).
• Technical Importance: This approach sought to reduce the cost and complexity of digital imaging hardware by removing a redundant memory component. (’527 Patent, col. 1:55-57).

Key Claims at a Glance

• The complaint does not identify any specific claims asserted from the ’527 Patent, instead incorporating by reference unfiled exhibits (Compl. ¶¶ 15-16). Independent claims 1 (an apparatus) and 8 (a method) are representative of the patent's scope.
• The essential elements of independent claim 1 include:
  • A "read control means" for reading a predetermined number of image lines from an A/D converter and generating a control signal.
  • A "memory means" for storing those image lines, with a capacity matching the "built-in memory device" of a JPEG compression means.
  • An "output control means" that responds to the control signal by reading an "image block" from the memory means and forwarding it to the built-in memory device.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," Issued December 6, 2005

The Invention Explained

• Problem Addressed: The patent explains that standard CMOS image sensors produce a "video style output" at a fixed rate, which is incompatible with the data interfaces of commercial microprocessors. This mismatch historically required "additional glue logic" and custom interface circuitry, diminishing the integration and cost advantages of using CMOS technology. (’790 Patent, col. 1:38-57).
• The Patented Solution: The invention describes a host interface, preferably integrated onto the same chip as the image sensor, that decouples the sensor from the processor. The interface uses a memory (such as a first-in-first-out, or FIFO, buffer) to store image data as it arrives from the sensor. When the amount of data in the memory reaches a certain level, a signal generator alerts the main processor (e.g., via an interrupt), which can then read the buffered data at its own pace. (’790 Patent, Abstract; col. 2:4-13).
• Technical Importance: This design allows for more direct and efficient integration of CMOS image sensors with general-purpose processors, reducing the need for intermediary logic and supporting the "system on a chip" design philosophy. (’790 Patent, col. 1:60-66).

Key Claims at a Glance

• The complaint does not identify any specific claims asserted from the ’790 Patent, instead incorporating by reference unfiled exhibits (Compl. ¶¶ 24-25). Independent claims 1, 8, and 15 are representative of the patent's scope.
• The essential elements of independent claim 1 include:
  • A "memory" for storing imaging array data and clocking signals at a rate determined by the clocking signals.
  • A "signal generator" for generating a signal for the processor system "in response to the quantity of data in the memory".
  • A "circuit for controlling the transfer of the data" from the memory at a rate determined by the processor system.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," Issued September 17, 2013 (Multi-Patent Capsule)

Technology Synopsis

As a divisional of the application that led to the ’790 Patent, the ’242 Patent addresses the same technical problem of interfacing an image sensor with a processor. The ’242 patent claims a method of processing imaging signals that involves receiving image data, storing it in a FIFO memory, updating a counter to track the amount of data, and generating a request (e.g., an interrupt or a bus request) for data transfer when the counter's value reaches a predetermined limit. (’242 Patent, Abstract; col. 2:1-25).

Asserted Claims

The complaint does not specify which claims of the ’242 Patent are asserted, again incorporating unfiled exhibits by reference (Compl. ¶¶ 33-34).

Accused Features

The complaint alleges infringement by "Exemplary Defendant Products" but does not identify the products or the specific features accused of infringing the ’242 Patent (Compl. ¶ 28).

III. The Accused Instrumentality

Product Identification

• The complaint does not identify any specific accused products or services. It refers generally to "Exemplary Defendant Products" and incorporates by reference external exhibits, which are not attached to the pleading, that purportedly identify these products. (Compl. ¶13).

Functionality and Market Context

• The complaint does not provide sufficient detail for analysis of the functionality or market context of any accused instrumentality.
• No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not contain narrative infringement allegations or claim charts. Instead, it states that infringement is detailed in Exhibits 4, 5, and 6, which are incorporated by reference but were not filed with the complaint (Compl. ¶¶ 16, 25, 34). As such, a claim chart summary cannot be constructed. The infringement allegations are limited to conclusory statements that the unspecified "Exemplary Defendant Products practice the technology claimed" by the patents-in-suit (Compl. ¶¶ 15, 24, 33).

• Identified Points of Contention:
  • ’527 Patent: The patent’s independent claims are written in means-plus-function format (e.g., "read control means"). A central dispute will involve identifying the structure in the accused products that allegedly performs the claimed functions and assessing whether that structure is the same as or equivalent to the specific embodiments disclosed in the patent (e.g., the control devices and memory shown in Fig. 2). (’527 Patent, col. 2:49-57). Another question is whether modern, highly-integrated systems contain the distinct "A/D converter" and "JPEG compression device" architecture that the patent's interface is designed to connect.
  • ’790 and ’242 Patents: These patents require a signal to be generated "in response to the quantity of data in the memory". A key technical question will be what evidence shows that the accused products' signaling mechanism is triggered by a quantitative data threshold in a buffer, as opposed to other events like an end-of-frame signal or a timer. The analysis may focus on whether a general-purpose processor interrupt system performs the specific function claimed in the patents.

V. Key Claim Terms for Construction

’527 Patent

• The Term: "image block"
• Context and Importance: Claim 1 requires the output control means to read an "image block" from memory for forwarding to the JPEG device. The definition of this term is critical because if it is construed narrowly to mean only a block formatted specifically for JPEG compression, it may not read on systems that transfer data in more generic chunks or for other purposes.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term itself does not inherently limit the size, format, or purpose of the data block.
  • Evidence for a Narrower Interpretation: The specification repeatedly links the "image block" to the requirements of the JPEG algorithm, stating the "basic compression unit is an image block of 8x8 pixels" and that the invention's memory is sized accordingly. (’527 Patent, col. 1:45-47). The abstract notes the image block is "of the same size of the compression unit required by the JPEG compression device." This context suggests the term may be limited to a specific format.

’790 Patent

• The Term: "in response to the quantity of data in the memory"
• Context and Importance: This phrase in claim 1 defines the condition that triggers the "signal generator". The infringement case for the ’790 and ’242 patents will likely depend on whether the accused products' data transfer requests are initiated based on a quantitative measure of buffer fullness.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party could argue this requires only a loose causal connection—if a buffer filling up eventually leads to a processor interrupt, the interrupt is "in response to the quantity of data".
  • Evidence for a Narrower Interpretation: The specification discloses a specific implementation using an "increment/decrement counter" whose output is compared to a "FIFO limit" to generate the signal. (’790 Patent, col. 6:11-15; Fig. 5). This disclosure of a direct quantitative comparison could be used to argue for a narrower construction that excludes systems triggered by other, non-quantitative events.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement of the ’790 and ’242 Patents. The factual basis alleged is that Defendant sells the accused products and distributes "product literature and website materials inducing end users and others to use its products in the customary and intended manner that infringes" the patents. (Compl. ¶¶ 22-23, 31-32).
• Willful Infringement: The complaint alleges willful infringement of the ’790 and ’242 Patents based on knowledge acquired from the date of service of the complaint itself. It alleges that "The service of this Complaint, in conjunction with the attached claim charts and references cited, constitutes actual knowledge of infringement." (Compl. ¶¶ 21, 30). No allegations of pre-suit knowledge are made.

VII. Analyst’s Conclusion: Key Questions for the Case

1. Evidentiary Sufficiency: The complaint's infringement allegations are wholly dependent on external exhibits that were not filed with the court. A threshold issue will be whether the pleading, which lacks any specific factual allegations tying an accused product to any patent claim, can survive a challenge for failure to state a plausible claim for relief.

2. Technological Obsolescence and Claim Scope: The patents claim priority to applications from 1999-2000 and describe specific hardware architectures for interfacing distinct components. A central question will be one of technical scope: can the claims, which describe interfacing discrete components like an A/D converter and a JPEG chip ('527 Patent) or a specific FIFO/interrupt logic ('790 Patent), be construed to cover modern System-on-a-Chip (SoC) devices where these functions may be deeply integrated or operate according to different principles?

3. Functional Mismatches: For the ’790 and ’242 patents, a key evidentiary question will be one of functional operation: does the accused technology’s data management system generate processor requests based on the specific "quantity of data in the memory", as required by the claims, or is signaling triggered by other, non-infringing events common in data processing, such as end-of-line or end-of-frame flags?