DCT

2:23-cv-00266

Unification Tech LLC v. Phison Electronics Corporation

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:23-cv-00266, E.D. Tex., 06/02/2023
  • Venue Allegations: Plaintiff alleges venue is proper under the alien-venue rule, as Defendant is not a resident of the United States and may be sued in any judicial district.
  • Core Dispute: Plaintiff alleges that Defendant’s solid-state drive (SSD) controllers infringe four U.S. patents related to methods for managing storage commands and identifying unused storage resources in non-volatile memory systems.
  • Technical Context: The technology concerns the internal architecture of SSD controllers, which are critical components for managing data flow and optimizing performance in modern solid-state storage used in everything from consumer electronics to enterprise data centers.
  • Key Procedural History: The complaint alleges that Plaintiff sent a letter to Defendant prior to filing suit, which identified the asserted patents and included claim charts demonstrating alleged infringement, a fact that may be central to the willfulness allegations.

Case Timeline

Date Event
2006-12-06 Priority Date (U.S. Patent Nos. 9,575,902; 11,061,825; 11,573,909)
2007-04-19 Priority Date (U.S. Patent No. 11,640,359)
2017-02-21 U.S. Patent No. 9,575,902 Issued
2021-07-13 U.S. Patent No. 11,061,825 Issued
2023-02-07 U.S. Patent No. 11,573,909 Issued
2023-05-02 U.S. Patent No. 11,640,359 Issued
2023-06-02 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,575,902

  • Patent Identification: U.S. Patent No. 9,575,902, "Apparatus, system, and method for managing commands of solid-state storage using bank interleave," issued February 21, 2017.
  • The Invention Explained:
    • Problem Addressed: The patent's background describes inefficiencies in solid-state storage, noting that writing data is often significantly slower than reading data and that conventional "write-in-place" methods can lead to premature wear and uneven use of memory cells (’825 Patent, col. 1:36-54).
    • The Patented Solution: The invention proposes a "bank interleave" controller that separates storage commands (e.g., read, write, erase) by type into different queues associated with different physical banks of memory. This architecture allows the controller to coordinate command execution in parallel, such that a long-duration command (like a write or erase) can execute on one bank while a short-duration command (like a read) executes concurrently on another bank, improving overall throughput ('825 Patent, col. 2:11-24; Abstract).
    • Technical Importance: This method of parallelizing different command types across memory banks addresses a fundamental performance bottleneck in solid-state storage, enabling higher-speed operation necessary for demanding applications ('825 Patent, col. 1:55-61).
  • Key Claims at a Glance:
    • The complaint asserts independent claim 1 (’902 Patent, Compl. ¶38).
    • The essential elements of independent claim 1, a method claim, include:
      • Receiving storage commands at respective command queues, each associated with one of two or more banks of a non-volatile solid-state storage device.
      • The storage commands include commands of a first type (e.g., Admin) and a second, different type (e.g., I/O).
      • Issuing commands from the first and second command queues such that execution of a first command overlaps in time with execution of a second command.
      • The execution duration of the first command is at least an order of magnitude greater than that of the second command.
      • Issuing commands from the first command queue in an order different than the order in which they were received.
    • The complaint reserves the right to assert additional claims (Compl. ¶38, fn. 1).

U.S. Patent No. 11,061,825

  • Patent Identification: U.S. Patent No. 11,061,825, "Apparatus, system, and method for managing commands of solid-state storage using bank interleave," issued July 13, 2021.
  • The Invention Explained:
    • Problem Addressed: This patent, part of the same family as the '902 Patent, addresses the same inefficiencies in solid-state storage command execution ('825 Patent, col. 1:36-54).
    • The Patented Solution: The invention is embodied as a system comprising two controllers. A first controller sorts incoming commands by type into separate queues for "management commands" and "other commands." A second controller receives commands from these queues, generates subcommands, and directs them to at least one bank of solid-state storage for parallel execution ('825 Patent, col. 2:11-24; Claim 1).
    • Technical Importance: As described for the '902 Patent, this architecture improves the operational efficiency and performance of solid-state storage systems.
  • Key Claims at a Glance:
    • The complaint asserts independent claim 1 ('825 Patent, Compl. ¶65).
    • The essential elements of independent claim 1, a system claim, include:
      • A first controller that directs at least one command to a plurality of queues, separating the command(s) based on command type.
      • The plurality of queues includes a first queue for "management commands" and a second queue for "other commands."
      • A second controller configured to receive commands from the queues, generate subcommands, and direct them to at least one bank of solid-state storage.
      • The solid-state storage itself.
    • The complaint reserves the right to assert additional claims (Compl. ¶65).

Multi-Patent Capsule: U.S. Patent No. 11,573,909

  • Patent Identification: U.S. Patent No. 11,573,909, "Apparatus, system, and method for managing commands of solid-state storage using bank interleave," issued February 7, 2023.
  • Technology Synopsis: This patent is from the same family as the '902 and '825 Patents. It describes a system with a controller architecture that separates storage commands by type (e.g., management vs. other commands) into different queues to enable parallel, interleaved execution across multiple memory banks, thereby improving performance.
  • Asserted Claims: The complaint asserts at least independent claim 1 (Compl. ¶88).
  • Accused Features: The complaint alleges that Phison's X1 SSD Platform and PS5018-E18 controllers, which implement the NVMe 1.4 interface, infringe by directing commands to separate queues for management and other commands, such as Admin Submission Queues and I/O Submission Queues (Compl. ¶¶ 90, 92).

Multi-Patent Capsule: U.S. Patent No. 11,640,359

  • Patent Identification: U.S. Patent No. 11,640,359, "Systems and methods for identifying storage resources that are not in use," issued May 2, 2023.
  • Technology Synopsis: This patent describes a method for a host system to inform a storage controller that certain data no longer needs to be preserved, without having to write over the data with zeros. The host sends an "empty-block directive" with a logical identifier; the controller then updates its internal mapping to reflect that the physical location is available for reuse and can return an "empty" indication for read requests to that logical identifier, improving efficiency and reducing write amplification.
  • Asserted Claims: The complaint asserts at least independent claim 1 (Compl. ¶109).
  • Accused Features: The complaint alleges that Phison's PS5026-E26 controller, which implements the NVMe 2.0 interface, infringes by using the "Dataset Management command" to deallocate logical blocks, which allegedly functions as the claimed "empty-block directive" (Compl. ¶¶ 111-113).

III. The Accused Instrumentality

  • Product Identification: The accused instrumentalities are Defendant’s SSD controllers, including but not limited to the Phison PS5026-E26 PCIe Gen5, PS5018-E18 PCIe Gen4, and X1 SSD Platform controllers (Compl. ¶¶ 36, 63, 86, 107). A product brochure for the PS5026-E26 controller is provided in the complaint, describing it as a high-performance solution for applications like gaming and high-end workstations (Compl. p. 11).
  • Functionality and Market Context: The accused products are semiconductor devices that serve as the "brain" of an SSD, managing communication between a host system and the underlying NAND flash memory. The complaint alleges these controllers implement industry standards such as NVM Express (NVMe) and Open NAND Flash Interface (ONFI) (Compl. ¶¶ 40, 46). These standards define protocols for command submission, queueing, and execution. Plaintiff alleges these controllers are incorporated into a wide variety of end-products sold in the U.S. by major brands (Compl. ¶18). A specifications table for the PS5026-E26 controller highlights its compliance with NVMe 2.0 (Compl. p. 13).

IV. Analysis of Infringement Allegations

U.S. Patent No. 9,575,902 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
receiving storage commands at respective command queues, each command queue associated with one of two or more banks of a non-volatile solid-state storage device... The accused controllers implement the NVMe 2.0 interface, which uses pre-allocated "Submission Queues" to receive commands from host software for a non-volatile memory subsystem. ¶40-41 col. 2:15-18
wherein the storage commands include storage commands of a first type received in an order at a first command queue...and storage commands of a second, different type, received in an order at a second command queue... The NVMe 2.0 interface defines different command types, such as Admin commands and I/O commands, which are submitted to distinct Admin Submission Queues and I/O Submission Queues. ¶43, 52 col. 2:35-40
issuing commands from the first and second command queues such that execution of a first command of the first type overlaps in time with execution of a second command of the second type. The NVMe 2.0 interface allegedly supports launching and executing multiple commands from a submission queue in parallel via an "Arbitration Burst," and the ONFI 5.0 interface allows separate logical units (LUNs) to operate on command sequences in parallel. ¶48-50 col. 2:25-29
wherein an execution duration of the first command is at least an order of magnitude greater than an execution duration of the second command. The complaint alleges that Admin Commands have an execution duration at least an order of magnitude greater than I/O commands. It also cites ONFI 5.0 timing tables where tADL (program) is 400 ns and tWHR (read status) is 80 ns. ¶51-52 col. 1:36-39
issuing commands from the first command queue in an order different than the order in which the commands were received at the first command queue. The complaint alleges that under the NVMe 2.0 interface, a controller may fetch commands in order from a Submission Queue but may execute them in any order. ¶53-54 col. 2:55-59
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the NVMe standard's "Submission Queues" (e.g., Admin vs. I/O queues) correspond to the claim limitation of "command queues associated with one of two or more banks." The patent's specification and figures suggest a physical architecture with distinct queues per memory bank, which raises the question of whether the NVMe standard's logical queueing mechanism meets this structural limitation.
    • Technical Questions: The complaint alleges an execution duration difference of "at least an order of magnitude" (10x). However, the specific timing data cited from the ONFI specification shows a 400 ns duration versus an 80 ns duration, a factor of 5x (Compl. p. 20). This raises an evidentiary question as to whether the "order of magnitude" limitation is met by the accused functionality as described.

U.S. Patent No. 11,061,825 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a first controller that directs at least one command to a plurality of queues, wherein the at least one command is separated into the plurality of queues based on a command type... The accused controllers implement the NVMe 1.4 interface, which allows host software to submit commands to one or more Submission Queues. These commands are separated by type. ¶67-68 col. 2:11-18
...the plurality of queues comprises a first queue configured to store management commands and a second queue configured to store other commands; The NVMe 1.4 interface allegedly includes separate queue types: Admin Submission Queues for administrative commands (management) and I/O Submission Queues for I/O commands like read and write (other commands). ¶69 col. 2:35-40
a second controller configured to receive the at least one command from the plurality of queues, generate subcommands based on the at least one command, and direct the subcommands to at least one bank of a solid-state storage... The accused controllers allegedly fetch commands from the Submission Queues, process them, and this processing generates subcommands directed to at least one bank of the solid-state storage. ¶71-72 col. 2:59-65
and the solid-state storage. The accused instrumentalities are either complete systems including solid-state storage (e.g., X1 SSD Platform) or are controllers configured for inclusion in such a system. The complaint includes a product brochure for the X1 SSD Platform, an enterprise SSD product (Compl. p. 25). ¶66, 70 col. 2:18-24
  • Identified Points of Contention:
    • Scope Questions: A dispute may arise over whether the accused controllers, which integrate multiple functions, embody the claimed "first controller" and "second controller" as distinct structural elements. The analysis will question whether the functional separation of command sorting and subcommand generation within a single accused controller satisfies the claim's requirement for two separate controllers.
    • Technical Questions: The complaint asserts on "information and belief" that the processing of commands generates and directs subcommands to memory banks (Compl. ¶72). What evidence the complaint provides to substantiate this internal operational step, which is not explicitly defined by the public-facing NVMe standard, will be a key factual question.

V. Key Claim Terms for Construction

  • Term: "command queue associated with one of two or more banks" ('902 Patent, Claim 1)

    • Context and Importance: Plaintiff's infringement theory maps the NVMe standard's logical Submission Queues to this physical architectural element. The viability of this mapping is critical, as Defendant may argue that NVMe queues are a host-interface construct, not physically tied to specific memory banks as depicted in the patent.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent abstract states the "bank interleave... directs one or more commands to two or more queues," which might be argued to support a functional rather than strictly physical association ('825 Patent, Abstract).
      • Evidence for a Narrower Interpretation: The patent’s detailed embodiment, particularly Figure 4A, illustrates a distinct set of command queues (Read Q, Write Q, Erase Q, Mgmt Q) for each physical bank (Bank-0, Bank-1, ... Bank-N), suggesting a specific one-to-one or one-to-many relationship between banks and queue sets ('825 Patent, Fig. 4A).

  • Term: "management commands" and "other commands" ('825 Patent, Claim 1)

    • Context and Importance: Plaintiff’s infringement theory equates NVMe "Admin" commands with "management commands" and NVMe "I/O" commands with "other commands." The definitions of these terms will determine if this is a permissible construction.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claims do not define these terms, which may support an interpretation based on their plain and ordinary meaning, allowing the NVMe command sets to be categorized accordingly.
      • Evidence for a Narrower Interpretation: The specification provides examples, stating management commands can include "a reset command to reset a bank and a read configuration register command," while other commands comprise "at least read, write, and erase commands" ('825 Patent, col. 2:48-55). This could be used to argue for a narrower definition limited to these specific examples.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that Defendant induces infringement by providing customers with products, technical documentation, product brochures, and other materials that allegedly instruct and encourage users to operate the accused controllers in an infringing manner (Compl. ¶¶ 55-56, 78-79, 99-100, 120-121).
  • Willful Infringement: The complaint alleges willful infringement based on both pre-suit and post-suit knowledge. Pre-suit knowledge is alleged to stem from a detailed letter with claim charts sent by Plaintiff to Defendant, while post-suit knowledge is based on the filing of the complaint itself (Compl. ¶¶ 30, 56, 79, 100, 121).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of architectural mapping: can the logical command queue structures of the NVMe standard, which govern host-controller communication, be construed to meet the patent claims' requirements for a physical architecture of command queues "associated with" specific, distinct memory banks?
  • A key evidentiary question will be one of quantitative proof: can Plaintiff demonstrate that the execution durations of different command types in the accused products differ by "at least an order of magnitude" as required by the '902 patent, particularly when the complaint’s own cited evidence appears to fall short of this 10x threshold?
  • A central claim construction question will be one of definitional scope: does the separation of commands into "Admin" and "I/O" categories under the NVMe standard align with the claimed separation of "management commands" and "other commands," or do the patent’s specific examples impose a narrower meaning that the accused products do not meet?