DCT
2:23-cv-00267
Unification Tech LLC v. Silicon Motion Inc. PURSUANT TO Court ORDER, DOCKET IN Lead Case 2:23CV266
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Unification Technologies LLC (Texas)
- Defendant: Silicon Motion Inc. (Taiwan)
- Plaintiff’s Counsel: Nelson Bumgardner Conroy PC
- Case Identification: 2:23-cv-00267, E.D. Tex., 06/02/2023
- Venue Allegations: Plaintiff alleges venue is proper because Defendant is not a resident of the United States and may therefore be sued in any judicial district pursuant to the alien-venue rule.
- Core Dispute: Plaintiff alleges that Defendant’s solid-state drive (SSD) controllers infringe four U.S. patents related to methods for managing storage commands and identifying unused storage resources in non-volatile memory systems.
- Technical Context: The technology concerns the internal management of commands within solid-state storage devices, a critical function for optimizing performance, efficiency, and endurance in modern computing hardware such as PCs, servers, and mobile devices.
- Key Procedural History: The complaint alleges that prior to filing the lawsuit, Plaintiff sent a letter to Defendant identifying the asserted patents and providing claim charts demonstrating infringement, which may be relevant to a future determination of willful infringement.
Case Timeline
| Date | Event |
|---|---|
| 2006-12-06 | Earliest Priority Date ('902, '825, '909 Patents) |
| 2007-09-22 | Earliest Priority Date ('359 Patent) |
| 2017-02-21 | U.S. Patent No. 9,575,902 Issues |
| 2021-07-13 | U.S. Patent No. 11,061,825 Issues |
| 2023-02-07 | U.S. Patent No. 11,573,909 Issues |
| 2023-05-02 | U.S. Patent No. 11,640,359 Issues |
| 2023-06-02 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,575,902 - "Apparatus, system, and method for managing commands of solid-state storage using bank interleave"
- Patent Identification: U.S. Patent No. 9,575,902, issued February 21, 2017. (Compl. ¶29).
The Invention Explained
- Problem Addressed: The patent's background describes that traditional "write-in-place" data handling techniques are inefficient for solid-state storage and can lead to premature failure due to uneven wear on memory cells. (’902 Patent, col. 1:36-54).
- The Patented Solution: The invention proposes a "bank interleave controller" for a solid-state storage device composed of two or more separately accessible memory "banks." The controller directs different types of commands (e.g., read, write, erase) to separate queues associated with each bank. This allows a long-duration command (like writing data) to execute on one bank concurrently with a fast-duration command (like reading data) on another bank, improving overall efficiency and throughput. (’902 Patent, Abstract; col. 2:11-24).
- Technical Importance: This method of parallelizing command execution across different memory banks was designed to overcome performance bottlenecks inherent in NAND flash operations, where different command types have vastly different execution times. (’902 Patent, col. 1:55-61).
Key Claims at a Glance
- The complaint asserts at least independent claim 1. (Compl. ¶43).
- Claim 1 is a method claim with the following essential elements:
- Receiving storage commands at respective command queues, each associated with one of two or more banks, with commands of a first type going to a first queue and commands of a second, different type going to a second queue.
- Issuing commands from the queues such that execution of a first command type overlaps in time with execution of a second command type.
- An execution duration of the first command is at least an order of magnitude greater than that of the second command.
- Issuing commands from the first command queue in an order different than the order in which they were received.
- The complaint expressly reserves the right to assert additional claims. (Compl. ¶43, fn. 1).
U.S. Patent No. 11,061,825 - "Apparatus, system, and method for managing commands of solid-state storage using bank interleave"
- Patent Identification: U.S. Patent No. 11,061,825, issued July 13, 2021. (Compl. ¶30).
The Invention Explained
- Problem Addressed: As with the parent '902 Patent, this invention addresses the inefficiency and potential for premature failure in solid-state storage systems that use traditional data management techniques. (’825 Patent, col. 1:36-54).
- The Patented Solution: The patent describes a system architecture featuring a "first controller" and a "second controller." The first controller directs incoming commands to separate queues based on their type, specifically separating "management commands" from "other commands." The second controller then takes commands from these queues, generates more detailed "subcommands" based on them, and directs those subcommands to the physical memory banks for execution. (’825 Patent, Abstract; col. 2:58-65).
- Technical Importance: This dual-controller architecture provides a structured way to separate high-level command sorting from low-level execution, enabling more granular control and parallelism in managing solid-state memory. (’825 Patent, col. 1:55-61).
Key Claims at a Glance
- The complaint asserts at least independent claim 1. (Compl. ¶70).
- Claim 1 is a system claim with the following essential elements:
- A first controller that directs commands to a plurality of queues based on command type, including a first queue for management commands and a second queue for other commands.
- A solid-state storage device that includes a second controller.
- The second controller is configured to receive commands from the queues, generate subcommands, and direct the subcommands to at least one bank of solid-state storage.
- The solid-state storage itself.
- The complaint reserves the right to identify additional claims. (Compl. ¶43, fn. 1).
U.S. Patent No. 11,573,909 - "Apparatus, system, and method for managing commands of solid-state storage using bank interleave"
- Patent Identification: U.S. Patent No. 11,573,909, issued February 7, 2023. (Compl. ¶31).
Technology Synopsis
This patent is a member of the same family as the ’902 and ’825 patents and is directed to similar technology for improving solid-state storage performance. The invention describes a system using a first controller to sort commands by type into distinct queues (management vs. other) and a second controller to process those commands into subcommands for execution on memory banks. (’909 Patent, Abstract).
Asserted Claims
The complaint asserts at least independent claim 1. (Compl. ¶92).
Accused Features
The accused functionality is the implementation of the NVMe 2.0 interface in SMI's controllers, which allegedly provides separate submission queues for administrative (management) and I/O (other) commands, mapping to the claimed invention. (Compl. ¶94, ¶96).
U.S. Patent No. 11,640,359 - "Systems and methods for identifying storage resources that are not in use"
- Patent Identification: U.S. Patent No. 11,640,359, issued May 2, 2023. (Compl. ¶32).
Technology Synopsis
This patent addresses the inefficiency of erasing data in non-volatile memory. The invention provides a method for a storage controller to receive a directive from a host computer that identifies data (via a logical identifier) that is no longer needed. The controller then updates its internal maps to mark the physical storage location as available for reuse, without needing to perform an immediate, time-consuming erase operation. (’359 Patent, Abstract).
Asserted Claims
The complaint asserts at least independent claim 1. (Compl. ¶113).
Accused Features
The accused feature is the implementation of the "Dataset Management Command" in the NVMe standard by SMI's controllers. This command, particularly its "Deallocate" function, allegedly serves as the claimed "empty-block directive," allowing the host to inform the controller that certain logical blocks are no longer in use and their physical space can be reclaimed. (Compl. ¶115-117).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities are Defendant's SMI SSD Controllers, including its Client, Enterprise, and Automotive SSD Controllers and FerriSSDs. Specific examples cited include the SM2268XT and the PCIe Gen4/NVMe Single Chip SSD Bx Series. (Compl. ¶41, ¶68, ¶90, ¶111).
Functionality and Market Context
- The accused products are semiconductor controllers that manage the operation of NAND flash memory in solid-state drives. (Compl. ¶2-3). The complaint alleges these controllers implement industry standards such as NVM Express (NVMe) 2.0 and Open NAND Flash Interface (ONFI) 5.0. (Compl. ¶45, ¶51). These standards allegedly provide the functionalities accused of infringement, such as using separate "Submission Queues" for different command types (Admin vs. I/O), executing commands in parallel across different "Logical Units" (LUNs), and using a "Dataset Management Command" to deallocate logical blocks. (Compl. ¶48, ¶55, ¶116-117). The complaint asserts Defendant is a "global leader" in this market, supplying controllers to major PC OEMs and technology companies. (Compl. ¶3, ¶17). An exemplary product brief for the accused FerriSSD is provided as visual evidence. (Compl. p. 25).
IV. Analysis of Infringement Allegations
'902 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| receiving storage commands at respective command queues... wherein the storage commands include storage commands of a first type received in an order at a first command queue... and storage commands of a second, different type, received in an order at a second command queue... | The accused controllers implement the NVMe 2.0 interface, which provides for separate Admin Submission Queues for administrative commands and I/O Submission Queues for I/O commands. | ¶45-48 | col. 2:15-24 |
| issuing commands from the first and second command queues such that execution of a first command of the first type overlaps in time with execution of a second command of the second type | The controllers implement ONFI 5.0, which allows separate Logical Units (LUNs) to "operate on arbitrary command sequences in parallel," and NVMe 2.0's "Arbitration Burst" feature, which launches multiple commands in parallel. | ¶54-55 | col. 2:20-24 |
| wherein an execution duration of the first command is at least an order of magnitude greater than an execution duration of the second command | ONFI 5.0 timing specifications show program operations (e.g., tADL at 400ns) taking an order of magnitude longer than other operations like write cycle time (tWC at 25ns). |
¶57 | col. 2:20-24 |
| issuing commands from the first command queue in an order different than the order in which the commands were received at the first command queue | The NVMe 2.0 standard allegedly allows the controller to fetch command entries in order from a Submission Queue but "execute those commands in any order." | ¶59 | col. 2:55-58 |
- Identified Points of Contention:
- Scope Questions: A potential issue is whether the logically defined "Submission Queues" of the NVMe standard meet the definition of "command queues associated with one of two or more banks" as recited in the claim, which could be interpreted as requiring a more direct physical association. Similarly, the court may need to determine if an ONFI "Logical Unit" (LUN) corresponds to the claimed "bank."
- Technical Questions: The complaint alleges that controllers "may execute" commands out of order. A factual question will be what evidence demonstrates that the accused products actually do "issue" commands from the queue in an order different from which they were received, as required by the final claim limitation.
'825 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a first controller that directs at least one command to a plurality of queues, wherein the at least one command is separated into the plurality of queues based on a command type of each command... and the plurality of queues comprises a first queue configured to store management commands and a second queue configured to store other commands | The accused controllers implement the NVMe 2.0 interface, which directs host commands to different queues based on type: "Admin Submission Queues" for management/administrative commands and "I/O Submission Queues" for other commands such as Read and Write. | ¶72-74 | col. 2:25-41 |
| a solid-state storage device comprising: a second controller configured to receive the at least one command from the plurality of queues, generate subcommands based on the at least one command, and direct the subcommands to at least one bank of a solid state storage; and | The accused controllers allegedly process commands from the NVMe queues and generate subcommands that are directed to banks of solid-state storage. The ONFI 5.0 standard, implemented by the controllers, provides for generating subcommands from a command, such as issuing a Read Page command to a selected LUN (bank). | ¶76-79 | col. 2:58-65 |
| the solid-state storage | The accused products include controllers configured for inclusion in systems with solid-state storage, or are integrated systems (like the FerriSSD) that include solid-state storage. | ¶71, ¶75 | col. 2:18-20 |
- Identified Points of Contention:
- Scope Questions: Claim 1 recites a "first controller" and a "second controller." The accused products are single-chip controllers. A central question for claim construction and infringement will be whether these terms require two distinct physical or structural components, or if they can be read to cover two logically separate functions performed by a single integrated processor.
- Technical Questions: The complaint alleges that the processing of commands "generates subcommands." A key factual question will be what evidence shows that the accused controllers' internal processing of NVMe commands results in the generation of distinct "subcommands" that are then directed to memory banks, as opposed to a more monolithic execution process. The complaint points to an ONFI specification diagram as evidence of this subcommand generation. (Compl. p. 33).
V. Key Claim Terms for Construction
The Term: "bank" (’902 Patent, Cl. 1; ’825 Patent, Cl. 1)
- Context and Importance: This term is fundamental to the patents' architecture of parallelized command execution. The infringement case rests on the theory that concepts from industry standards, such as an ONFI "Logical Unit (LUN)" or an NVMe "namespace," meet the definition of a "bank." Practitioners may focus on this term because its scope will determine whether the logical partitions in the accused devices can be mapped onto the patent's potentially physical description.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification defines a bank functionally as being "separately accessible and each bank including two or more solid-state storage elements accessed in parallel." (’825 Patent, col. 2:18-22). This functional language may support an interpretation that covers any independently addressable and parallel-accessible memory region.
- Evidence for a Narrower Interpretation: Figure 2B of the patents depicts distinct hardware units labeled "Bank 0," "Bank 1," through "Bank N" (e.g., ’825 Patent, Fig. 2B, items 214a-n), which may suggest the term is limited to physically distinct partitions of the memory array.
The Term: "first controller" and "second controller" (’825 Patent, Cl. 1)
- Context and Importance: The structure of claim 1 requires two distinct controllers performing different functions (command sorting vs. subcommand generation). The accused products are single-chip controllers. The viability of the infringement claim may depend on whether these two "controllers" can be construed as logically distinct functional modules within a single processor.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent describes the controllers by their functions: the first "directs" commands to queues, and the second "receives" commands, "generates subcommands," and "directs the subcommands." (’825 Patent, Cl. 1). This functional claiming style could support an interpretation where one physical device performing these two distinct sets of functions satisfies the limitation. The specification also shows a "Solid-State Storage Device Controller" (202) containing multiple other controllers (104a-n), suggesting a hierarchical or modular view. (’825 Patent, Fig. 2B).
- Evidence for a Narrower Interpretation: The claim language uses "a first controller" and "a second controller," which may imply structural separateness under claim differentiation principles. A defendant could argue that if the patentee meant a single controller performing two functions, the claim would have been drafted that way.
VI. Other Allegations
- Indirect Infringement: The complaint alleges inducement of infringement, stating that Defendant provides its customers with products along with technical documentation, product briefs, and advertisements that instruct and encourage the use of the accused functionalities (e.g., the features of the NVMe and ONFI standards). (Compl. ¶60-61, ¶82-83, ¶103-104, ¶124-125).
- Willful Infringement: The complaint alleges willful infringement based on Defendant's alleged pre-suit knowledge of the patents. This knowledge is purportedly established by a letter and detailed claim charts sent from Plaintiff to Defendant before the lawsuit was filed. (Compl. ¶35, ¶62, ¶84, ¶105, ¶126).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of architectural scope: can the "first controller" and "second controller" recited in the system claims be construed to cover logically distinct functional modules within the accused single-chip SSD controllers, or do the claims require physically separate structures?
- A second central issue will be one of terminological mapping: can the term "bank," as defined and illustrated in the patent specifications in the context of physical memory arrays, be interpreted broadly enough to read on the logically defined "Logical Units" (LUNs) and "namespaces" of the ONFI and NVMe standards implemented by the accused products?
- A key evidentiary question will be one of operational proof: what evidence will be presented to demonstrate that the accused controllers, which allegedly "may execute" commands out of order, actually "issue" commands from their queues in an order different from which they were received, as required by claim 1 of the '902 patent?