DCT

2:23-cv-00299

Daedalus Prime LLC v. Taiwan Semiconductor Mfg Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:23-cv-00299, E.D. Tex., 06/22/2023
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation, which may be sued in any judicial district.
  • Core Dispute: Plaintiff alleges that semiconductor devices manufactured by Defendant using its advanced process nodes (16nm and smaller) infringe five U.S. patents related to semiconductor structure and fabrication methods.
  • Technical Context: The technology at issue involves fundamental fabrication techniques for advanced integrated circuits, such as forming conductive interconnects and capping transistor gates, which are critical for performance and reliability in modern microprocessors.
  • Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date Event
2011-09-30 Earliest Priority Date for ’699 and ’347 Patents
2011-11-04 Earliest Priority Date for ’183 Patent
2011-12-29 Earliest Priority Date for ’626 Patent
2013-12-19 Earliest Priority Date for ’354 Patent
2015-12-01 ’699 Patent Issued
2016-11-08 ’347 Patent Issued
2017-09-00 Approximate launch of Apple iPhone 8/X (incorporating A11 SoC)
2018-09-00 Approximate launch of Apple iPhone XS/XR (incorporating A12 SoC)
2019-09-00 Approximate launch of Apple iPhone 11 (incorporating A13 SoC)
2020-03-17 ’626 Patent Issued
2020-07-28 ’183 Patent Issued
2020-09-00 Approximate launch of Samsung Galaxy S20 FE (incorporating Snapdragon 865 SoC)
2020-09-29 ’354 Patent Issued
2021-09-00 Approximate launch of Apple iPhone 13 (incorporating A15 SoC)
2022-09-00 Approximate launch of Apple iPhone 14 (incorporating A16 SoC)
2023-06-22 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,727,183 - "Methods and apparatuses to form self-aligned caps"

  • Issued: July 28, 2020

The Invention Explained

  • Problem Addressed: The patent’s background section describes how metal capping layers, used to prevent electromigration in interconnect lines, can grow laterally beyond the width of the line itself (’183 Patent, col. 1:46-53). This lateral growth reduces the spacing between adjacent lines and increases "line edge roughness," both of which can degrade the reliability and performance of an integrated circuit (’183 Patent, col. 1:63-col. 2:7).
  • The Patented Solution: The invention proposes recessing the top of a conductive line to form a channel that is self-aligned to the line itself. A capping layer is then deposited within this channel (’183 Patent, Abstract). By containing the cap growth within the recessed channel, the invention aims to prevent lateral expansion, thereby preserving the critical line-to-line spacing and reducing line edge roughness (’183 Patent, col. 3:56-col. 4:2).
  • Technical Importance: This approach provided a method to improve the reliability of interconnects at advanced technology nodes where the distance between conductive lines is extremely small and sensitive to manufacturing variations.

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶35).
  • Claim 1 is directed to an integrated circuit structure with the following essential elements:
    • A dielectric layer comprising silicon, oxygen, and carbon.
    • A conductive structure within the dielectric layer, which itself comprises:
      • A first conductive material of copper, with its upper surface recessed below the upper surface of the dielectric layer.
      • A second conductive material of cobalt on top of the copper, having an upper surface with a portion substantially co-planar with the dielectric layer's upper surface, and a curved corner below that portion.
      • The copper and cobalt materials have the same width where they meet.
    • A barrier layer of tantalum partially surrounding the conductive structure.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 9,202,699 - "Capping dielectric structure for transistor gates"

  • Issued: December 1, 2015

The Invention Explained

  • Problem Addressed: The patent addresses the fabrication of capping structures on transistor gates, particularly in non-planar transistor architectures like FinFETs (’699 Patent, col. 1:8-12). Conventional deposition processes may fail to completely fill the narrow, high-aspect-ratio recesses created on top of gate electrodes, leading to voids that can cause short circuits and device failure (’699 Patent, col. 6:15-20).
  • The Patented Solution: The invention claims a method for forming a capping structure using a "high density plasma" (HDP) deposition process. This process is described as being capable of depositing a substantially void-free dielectric material into the recess on a recessed non-planar transistor gate, thereby creating a reliable capping structure (’699 Patent, Abstract; col. 2:18-24).
  • Technical Importance: The method provided a way to reliably fabricate critical capping structures for advanced FinFETs, which is essential for manufacturing high-performance, high-density processors.

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶45).
  • Claim 1 is directed to a manufacturing method with the following essential steps:
    • Forming a sacrificial non-planar transistor gate over a non-planar transistor fin.
    • Depositing a dielectric layer and forming gate spacers.
    • Forming a source/drain region.
    • Removing the sacrificial gate to form a gate trench.
    • Forming a gate dielectric and depositing conductive gate material in the trench.
    • Removing a portion of the conductive material to form a recess.
    • Forming a capping dielectric structure in the recess via high density plasma deposition.
    • Forming at least one more dielectric material over the structure.
    • Forming a contact opening through the dielectric material to expose the source/drain region.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 9,490,347 - "Capping dielectric structure for transistor gates"

  • Issued: November 8, 2016
  • Technology Synopsis: Belonging to the same patent family as the ’699 patent, the ’347 patent addresses the same technical challenge of forming void-free capping structures on recessed transistor gates (’347 Patent, Abstract). It claims a method of fabricating a transistor gate, comprising steps such as forming a gate electrode, recessing it, and then using a high density plasma process to deposit a capping dielectric structure within the recess (’347 Patent, col. 9:1-21).
  • Asserted Claims: Independent claim 1 (Compl. ¶56).
  • Accused Features: The complaint accuses TSMC’s 10nm node products and processes, with the Apple A11 and A10X SoCs cited as examples (Compl. ¶¶ 25, 55, 57).

U.S. Patent No. 10,790,354

  • Technology Synopsis: This patent addresses the issue of transistor layout density, which is limited by the need to create large gate "end-caps" to accommodate for potential misalignment during lithography (’354 Patent, col. 3:1-11). The invention describes an integrated circuit structure with "gate edge isolation structures" that are self-aligned to the transistor fins and gate, defining the gate boundaries precisely without requiring extra space for mask registration error, thereby enabling tighter transistor packing (’354 Patent, Abstract; col. 4:1-12).
  • Asserted Claims: Independent claim 1 (Compl. ¶67).
  • Accused Features: The complaint accuses TSMC’s 4nm and 5nm node products and processes, exemplified by the Apple A16 and A15 SoCs (Compl. ¶66).

U.S. Patent No. 10,593,626

  • Technology Synopsis: This patent concerns the fabrication of multilevel interconnects using a dual damascene process. The background describes the difficulty of post-patterning cleaning, which must remove hard masks and polymers without damaging sensitive underlying materials like low-k dielectrics or tungsten contacts (’626 Patent, col. 1:43-56). The invention claims a specific integrated circuit structure comprising a first interconnection line, a low-k interlayer dielectric (ILD) material made of carbon, silicon, and oxygen, and a second interconnection line connected via a conductive via, all with specific geometric relationships (’626 Patent, Abstract; Claim 20).
  • Asserted Claims: Independent claim 20 (Compl. ¶78).
  • Accused Features: The complaint accuses TSMC’s 7nm node products and processes, with the Apple A12 SoC cited as an example (Compl. ¶77).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are semiconductor devices, integrated circuits, and other products manufactured by TSMC using any of its 16nm and smaller technology nodes, including 16nm, 12nm, 10nm, 7nm, 6nm, 5nm, and 4nm (Compl. ¶20). Specific examples cited include Systems-on-Chip (SoCs) fabricated for customers like Apple (e.g., A11, A12, A13, A15, A16 SoCs) and Qualcomm (e.g., Snapdragon 865, Snapdragon 439 SoCs) (Compl. ¶¶ 22-26).

Functionality and Market Context

The accused products are advanced microprocessors that serve as the core processing units for a wide range of high-volume consumer electronics, including smartphones, tablets, and other devices sold by companies like Apple and Samsung (Compl. ¶¶ 4, 22-26). The complaint alleges that TSMC is the world's largest semiconductor foundry and that two-thirds of its revenue comes from the United States (Compl. ¶9). The complaint includes an image from an analysis of a Qualcomm Snapdragon 865 5G SoC as evidence for infringement of the ’183 Patent (Compl. p. 17). An image from an analysis of a Qualcomm Snapdragon 439 SoC is provided as evidence for infringement of the ’699 Patent (Compl. p. 20).

IV. Analysis of Infringement Allegations

’183 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
an integrated circuit structure, comprising: a dielectric layer having an upper surface, the dielectric layer comprising silicon, oxygen and carbon; The accused devices, such as the Qualcomm Snapdragon 865 5G SoC, allegedly include a dielectric layer containing silicon, oxygen, and carbon. A provided elemental analysis graph purports to show the presence of Si, O, and C (Compl. p. 17). ¶37 col. 15:30-33
a conductive structure in the dielectric layer, the conductive structure comprising: a first conductive material comprising copper, the first conductive material having an upper surface, with a portion of the upper surface of the first conductive material below a portion of the upper surface of the dielectric layer; The accused devices allegedly have a conductive structure made of copper that is recessed below the surrounding dielectric layer. An annotated micrograph shows a region labeled "Cu" recessed within a structure (Compl. p. 17). ¶37 col. 16:5-10
and a second conductive material on the upper surface of the first conductive material, the second conductive material comprising cobalt, wherein the first conductive material and the second conductive material have a same width at a location where the first conductive material and the second conductive material meet, A second material, identified as cobalt ("Co"), is allegedly present on top of the copper. This cobalt layer is alleged to have the same width as the copper layer where they meet. The micrograph shows a layer labeled "Co" on top of the "Cu" layer (Compl. p. 17). ¶37 col. 9:8-14
wherein the second conductive material has an upper surface having a portion substantially co-planar with the portion of the upper surface of the dielectric layer, and wherein the upper surface of the second conductive material has a curved corner below the portion of the upper surface of the dielectric layer; The cobalt layer allegedly has an upper surface that is substantially co-planar with the dielectric layer and includes a curved corner. ¶37 col. 14:38-42
and a barrier layer partially surrounding the conductive structure, the barrier layer comprising tantalum. A barrier layer made of tantalum is alleged to surround the conductive structure. The provided micrograph identifies a layer labeled "Ta" lining the trench containing the copper and cobalt (Compl. p. 17). ¶37 col. 16:42-47

Identified Points of Contention (’183 Patent)

  • Scope Questions: The definition of geometric terms such as "substantially co-planar" and "curved corner" may be a central point of dispute. The litigation may explore whether the degree of planarity and the specific shape of the corner in the accused TSMC products fall within the scope of these terms as construed by the court.
  • Technical Questions: The complaint's infringement theory relies on its analysis of the accused SoC, which identifies specific materials (Cu, Co, Ta) and structures. A technical question will be whether discovery and expert analysis confirm the presence and arrangement of these materials as alleged, and whether the provided micrograph (Compl. p. 17) accurately represents the structure across all accused devices.

’699 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a method comprising: forming a sacrificial non-planar transistor gate over a non-planar transistor fin; The complaint alleges that TSMC's 12nm manufacturing process, used for products like the Qualcomm Snapdragon 439 SoC, employs a replacement gate process that involves forming a sacrificial gate over a transistor fin. A provided image shows a structure labeled "Si fin" (Compl. p. 20). ¶47 col. 4:58-62
depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor fin; forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate; The accused process allegedly includes depositing a dielectric and forming gate spacers adjacent to the sacrificial gate. ¶47 col. 5:10-21
removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin; The accused process allegedly removes the sacrificial gate to create a trench for the permanent gate material. The provided image depicts a final structure with a "gate" located between source/drain regions (Compl. p. 20). ¶47 col. 5:50-55
depositing conductive gate material within the gate trench; removing a portion of the conductive gate material to form a recess between the non-planar transistor gate spacers; The accused process allegedly fills the trench with conductive material and then etches it back to form a recess. ¶47 col. 6:1-6
forming a capping dielectric structure within the recess by high density plasma depositing a dielectric material; The complaint alleges, on information and belief, that TSMC uses Applied Materials equipment to perform a high density plasma deposition step to form a capping dielectric structure. ¶¶47, 49 col. 6:10-24
forming at least one dielectric material over the source/drain region, the non-planar transistor gate spacers, and the capping dielectric structure; and forming a contact opening ... to expose at least a portion of the source/drain region. The accused process allegedly concludes with depositing additional dielectric layers and etching contact openings to the source/drain regions. The provided image shows layers labeled "SiON" and "SiWS" above the gate and source/drain regions (Compl. p. 20), which may correspond to these dielectric and contact structures. ¶47 col. 7:1-9

Identified Points of Contention (’699 Patent)

  • Scope Questions: The meaning of "high density plasma depositing" will be a critical issue for claim construction. The parties may dispute what specific process parameters (e.g., plasma density, pressure, temperature) are required to meet this limitation.
  • Technical Questions: A central evidentiary question will be whether TSMC's manufacturing process actually performs the claimed "high density plasma depositing" step to form the capping structure. The complaint bases this allegation on "information and belief" and public reports about TSMC's equipment suppliers (Compl. ¶49), suggesting that direct evidence from discovery will be necessary to substantiate this element.

V. Key Claim Terms for Construction

’183 Patent

  • The Term: "substantially co-planar"
  • Context and Importance: This term describes the vertical alignment between the top of the cobalt capping layer and the top of the surrounding dielectric layer. Its construction is critical because infringement will depend on how much deviation from perfect planarity is permitted. Practitioners may focus on this term because manufacturing processes rarely achieve perfect flatness, and the scope of "substantially" will likely be contested.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification's focus is on containing the cap within the recessed channel to prevent lateral growth, which may suggest that the precise degree of co-planarity is less important than the overall containment function.
    • Evidence for a Narrower Interpretation: The figures, such as Figure 2H, depict a relatively flat, highly co-planar surface between the capping layer (215) and the dielectric (203). This could be used to argue for a stricter standard of planarity.

’699 Patent

  • The Term: "high density plasma depositing"
  • Context and Importance: This term defines the specific technology used to form the capping dielectric structure. The infringement allegation for this method claim hinges on proving TSMC uses this particular type of deposition. Practitioners may focus on this term because there are many types of deposition techniques (e.g., PVD, CVD, ALD), and even within plasma-based methods, "high density" may have a specific technical meaning that TSMC's process may or may not meet.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent does not define the term with specific numerical ranges for plasma density or other parameters, which could support a construction based on the general understanding of HDP in the art at the time.
    • Evidence for a Narrower Interpretation: The specification describes a detailed HDP process with exemplary parameters, including chamber pressure, RF power ranges, and reactive gases (’699 Patent, col. 7:25-col. 8:52, via its parent application). A party could argue these examples implicitly define or limit the scope of the claimed term.

VI. Other Allegations

Indirect Infringement

The complaint alleges that TSMC induces infringement by its customers, such as Apple and Qualcomm, who import and sell downstream products (e.g., smartphones) containing the allegedly infringing chips (Compl. ¶17). It also alleges that TSMC contributes to infringement by manufacturing and selling the chips, which are alleged to be a material part of the patented inventions and not staple articles of commerce suitable for substantial noninfringing use (Compl. ¶19).

Willful Infringement

The complaint alleges willful infringement based on TSMC having received actual notice of the asserted patents "at least by way of a letter to TSMC dated June 22, 2023," the same day the complaint was filed (Compl. ¶15). The filing of the complaint is also asserted as constituting notice.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of evidentiary proof: The complaint relies on reverse engineering and "information and belief" to allege the specific material compositions, structural features, and manufacturing steps used by TSMC in its most advanced and proprietary process nodes. A key question for the case will be whether the evidence obtained during discovery substantiates these detailed allegations, particularly regarding the use of a "high density plasma depositing" process (’699 Patent) and the precise geometry and material makeup of the interconnect caps (’183 Patent).
  • The case will also likely involve a central dispute over definitional scope: The infringement analysis for the asserted product claims will depend on the court's construction of qualitative, geometric terms like "substantially co-planar" and "curved corner" (’183 Patent). Whether TSMC's mass-produced structures, with their inherent manufacturing variations, fall within the scope of these terms will be a critical question for the court.
  • A third key question will be one of process identity: For the asserted method claims, the plaintiff must prove that TSMC’s fabrication process includes the specific sequence of steps claimed. The case may turn on whether there are material differences between TSMC’s actual manufacturing flow and the steps recited in the patents, such as the method for forming the capping dielectric structure (’699 and ’347 Patents).