InnoMemory LLC v. Micro Star Intl Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory LLC (Texas)
  • Defendant: Micro-Star International Co. Ltd. (Taiwan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:23-cv-00337, E.D. Tex., 07/20/2023
• Venue Allegations: Venue is asserted based on the defendant being a foreign corporation.
• Core Dispute: Plaintiff alleges that certain of Defendant's products infringe a patent related to methods for reducing power consumption in memory devices by selectively refreshing portions of a memory array.
• Technical Context: The technology addresses power management in dynamic random-access memory (DRAM), a critical consideration for extending battery life and standby time in portable electronic devices.
• Key Procedural History: Plaintiff is the assignee of the patent-in-suit. The patent is a continuation of a prior application that issued as U.S. Patent No. 6,618,314. The complaint's infringement allegations rely on claim charts provided in an exhibit that was not included with the filed complaint document.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - Method and architecture for reducing the power consumption for memory devices in refresh operations, Issued June 6, 2006

The Invention Explained

• Problem Addressed: The patent describes a problem with conventional dynamic semiconductor memory devices, which are often configured to refresh all memory cells even when in a low-power standby mode. For battery-powered devices where only a portion of the memory needs to be retained, refreshing the entire array and activating all associated support circuitry consumes unnecessary power, reducing standby time ('960 Patent, col. 1:36-56). A specific disadvantage noted is that conventional systems activate the periphery array circuits for all quadrants of the memory, even when less than the full array requires refreshing ('960 Patent, col. 2:27-30).
• The Patented Solution: The invention proposes a method and architecture to reduce power consumption by enabling more granular control over memory refresh operations. It divides the memory array into multiple sections and uses control signals to selectively enable or disable the "periphery array circuitry" for each section independently ('960 Patent, col. 3:25-33). This allows the device to perform background operations, such as refresh, only on the necessary sections, leaving the support circuits for other sections inactive to conserve power ('960 Patent, Abstract; Fig. 3).
• Technical Importance: This approach provides a way to significantly lower the standby power consumption of memory devices, which is critical for extending the operational life of battery-powered portable terminals like mobile phones ('960 Patent, col. 1:39-48).

Key Claims at a Glance

• The complaint alleges infringement of "exemplary method claims" without identifying them specifically (Compl. ¶11, 13). The analysis below focuses on independent method claim 1 as a representative example.
• Independent Claim 1 recites a method for reducing power consumption with the following essential elements:
  • Controlling background operations in each of a plurality of sections of a memory array in response to one or more control signals.
  • The control signals are generated in response to a "programmable address signal."
  • The background operations can be enabled simultaneously in two or more sections "independently of any other section."
  • Presenting the control signals and one or more "decoded address signals" to "one or more periphery array circuits" of the sections.
• The complaint states that "numerous other devices that infringed the claims of the '960 Patent have been used," suggesting a potential reservation of rights to assert additional claims (Compl. ¶11).

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products by name. It refers generally to "Exemplary Defendant Products" that are purportedly identified in charts within an "Exhibit 2" attached to the complaint (Compl. ¶11, 13). This exhibit was not provided.

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the accused products' functionality or market context. It makes only the conclusory allegation that the "Exemplary Defendant Products practice the method claimed by the '960 Patent" (Compl. ¶13).

IV. Analysis of Infringement Allegations

The complaint alleges that infringement is detailed in claim charts in Exhibit 2, which is not available for review (Compl. ¶13, 14). Without these charts or a more detailed narrative in the complaint body, a substantive analysis of the infringement allegations is not possible. The complaint's theory rests on the assertion that Defendant's products "satisfy all elements of the Exemplary '960 Patent method Claims" (Compl. ¶13). No probative visual evidence provided in complaint.

• Identified Points of Contention: Based on the language of claim 1, the dispute may center on several technical and legal questions:
  • Technical Question: What evidence demonstrates that the accused products' memory controllers can independently enable and disable the "periphery array circuits" for different memory sections as required by the claim? The core of the dispute will likely involve a technical comparison between the architecture disclosed in the patent and the actual implementation within Defendant's products.
  • Scope Question: How does the "programmable address signal" manifest in the accused products? The case may turn on whether a signal that is, for example, pre-configured at the system level rather than directly user-programmable falls within the scope of this claim term.
  • Functional Question: Does the power-saving mechanism in the accused products operate by controlling background operations "independently of any other section," or is there a different method of power reduction at play that does not map onto the claimed method?

V. Key Claim Terms for Construction

The Term: "programmable address signal" (from claim 1)

• Context and Importance: This term is central to the invention's claimed functionality of selecting which memory sections to refresh. The infringement analysis will depend on whether the accused products contain a feature that can be characterized as a "programmable address signal." Practitioners may focus on this term because its construction will define the required level of programmability and control.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Claim 1 itself does not specify the source or nature of the signal, only that it is "programmable." The specification describes a "refresh address register" (138) that stores a "refresh block address" (AR1), which could be interpreted as any signal that can be set to designate which blocks are targeted for a background operation ('960 Patent, col. 4:56-61).
  • Evidence for a Narrower Interpretation: The embodiments show a specific implementation where a "refresh address register" is loaded with an address (AR1) via a dedicated input, which in turn generates a "refresh block" signal (REF_BLK) ('960 Patent, col. 4:56-65; Fig. 3). A party could argue this implies a requirement for a distinct, modifiable register that stores an address for the express purpose of selecting refresh sections.

The Term: "periphery array circuits" (from claim 1)

• Context and Importance: Infringement requires showing that these specific types of circuits are controlled on a per-section basis. The definition of this term will dictate the scope of evidence Plaintiff must produce regarding the circuitry in Defendant's products.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Claim 5 provides a list of exemplary circuits, stating they "each comprise one or more circuits from the group consisting of sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" ('960 Patent, col. 11:65-col. 12:2). The use of "comprise" and "group consisting of" could support an interpretation that includes these examples and potentially other functionally similar support circuits.
  • Evidence for a Narrower Interpretation: A defendant may argue that the term is limited by the detailed embodiment shown in Figure 5, which illustrates a specific combination and arrangement of a wordline driver circuit (160), an equalization circuit (162), sense amplifiers (164), and a column select multiplexer (166) ('960 Patent, Fig. 5; col. 6:51-54). This could support an argument that control over a specific set of these interconnected circuits is required.

VI. Other Allegations

• Indirect Infringement: The complaint does not plead a count for either induced or contributory infringement. The allegations are limited to direct infringement by the Defendant and its employees (Compl. ¶11, 12).
• Willful Infringement: The complaint does not contain an explicit allegation of willful infringement. It does, however, request that the case be "declared exceptional within the meaning of 35 U.S.C. § 285" and seeks an award of attorneys' fees, but it does not plead facts concerning pre- or post-suit knowledge of the patent by the Defendant (Compl. ¶E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

• A primary issue will be one of evidence and technical proof: The complaint's bare-bones nature shifts the entire weight of the infringement case to evidence that is not yet on the record. The key question is whether Plaintiff can produce technical evidence demonstrating that the specific architecture and operation of Defendant's products map onto the elements of the asserted claims, particularly the independent control of "periphery array circuits" for discrete memory sections.
• The case will also likely hinge on a question of definitional scope during claim construction. The outcome may depend on whether the term "programmable address signal" is construed broadly to cover any system-level mechanism for selecting memory sections for refresh, or more narrowly to require a discrete, modifiable register-based implementation as depicted in the patent's embodiments.