DCT

2:23-cv-00338

InnoMemory LLC v. Pioneer Corp

Key Events
Complaint
complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:23-cv-00338, E.D. Tex., 07/20/2023
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation and has committed acts of patent infringement resulting in harm within the district.
  • Core Dispute: Plaintiff alleges that certain unidentified products made by Defendant infringe a patent related to methods for reducing power consumption in memory devices during refresh operations.
  • Technical Context: The technology concerns power-saving techniques for dynamic random-access memory (DRAM), a critical consideration for extending battery life in mobile and portable electronic devices.
  • Key Procedural History: The patent-in-suit is a continuation of an earlier U.S. application that issued as U.S. Patent No. 6,618,314, which may be relevant for determining the effective priority date of the asserted claims.

Case Timeline

Date Event
2002-03-04 '960 Patent Priority Date (Filing date of parent application)
2003-07-29 '960 Patent Application Filing Date
2006-06-06 '960 Patent Issue Date
2023-07-20 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

  • Patent Identification: U.S. Patent No. 7,057,960, “Method and architecture for reducing the power consumption for memory devices in refresh operations,” issued June 6, 2006. (Compl. ¶8-9; ’960 Patent, (45), (54)).

The Invention Explained

  • Problem Addressed: The patent describes a problem with conventional memory devices, particularly in battery-powered applications, where standby power is consumed by refreshing the entire memory array even when only a portion of the stored data needs to be retained (’960 Patent, col. 1:49-56). A specific disadvantage noted is that in conventional systems, the support circuitry for all memory sections (quadrants) is activated during a refresh cycle, even if only a subset of the memory is being refreshed, leading to unnecessary power use (’960 Patent, col. 2:26-29).
  • The Patented Solution: The invention discloses a method and architecture for reducing power consumption by selectively refreshing only designated sections of a memory array. This is achieved by using control signals (e.g., REF0-REFn) to enable the "periphery array circuitry" (such as wordline drivers and sense amplifiers) only for the specific memory sections undergoing a refresh operation, while keeping the circuitry for other sections disabled (’960 Patent, Abstract; col. 3:26-33). This selective activation is controlled by a programmable signal that determines which memory blocks are to be maintained.
  • Technical Importance: This approach allows for a significant reduction in standby current, which directly impacts and can extend the continuous standby time for battery-powered portable terminals such as mobile phones (’960 Patent, col. 1:35-48).

Key Claims at a Glance

  • The complaint does not identify specific asserted claims, instead referring to "the Exemplary ’960 Patent Claims" detailed in an exhibit that was not provided with the complaint (Compl. ¶11, ¶13). As a representative example, independent claim 1 is analyzed below.
  • Independent Claim 1:
    • A method for reducing power consumption during background operations in a memory array with a plurality of sections, comprising the steps of:
    • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
    • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.

III. The Accused Instrumentality

Product Identification

  • The complaint does not name any specific accused products. It refers to "Exemplary Defendant Products" that are purportedly identified in Exhibit 2, which is not included with the complaint filing (Compl. ¶11, ¶13).

Functionality and Market Context

  • The complaint provides no details regarding the technical functionality, operation, or market context of the accused products.

IV. Analysis of Infringement Allegations

The complaint’s substantive infringement allegations are contained entirely within claim charts in an external "Exhibit 2," which was not provided (Compl. ¶13). The complaint itself contains only conclusory statements that the "Exemplary Defendant Products practice the method claimed by the ’960 Patent" (Compl. ¶13). Due to the lack of specific factual allegations or an infringement chart, a detailed analysis is not possible.

  • Identified Points of Contention: Based on an analysis of representative Claim 1 of the ’960 Patent, the following points may become central to the infringement dispute once factual allegations are presented.
    • Scope Questions: A potential dispute may arise over the meaning of "programmable address signal." The question for the court could be whether this term requires a user- or system-configurable register, as described in embodiments in the specification, or if it can be construed more broadly to cover a fixed, manufacturer-set configuration that selects certain memory sections for partial refresh.
    • Technical Questions: A key evidentiary question will be whether the accused products actually implement power saving by selectively enabling and disabling "periphery array circuits" for different sections of memory. The complaint provides no factual basis to assess whether the accused products perform this specific technical function as required by the claim, as opposed to achieving power savings through other means.

V. Key Claim Terms for Construction

  • The Term: "periphery array circuits"

  • Context and Importance: This term defines the specific components that the patented method controls to achieve power savings. The infringement analysis will depend on whether the accused products contain structures that meet this definition and are controlled in the claimed manner.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification suggests the term is a category, stating that periphery array circuits "each comprise one or more circuits from the group consisting of sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" (’960 Patent, col. 8:65-col. 9:2). This could support an interpretation that the term covers any of these types of standard memory support circuits.
    • Evidence for a Narrower Interpretation: The detailed description and figures provide specific implementations, such as the wordline driver circuit 160 and sense amplifiers 164a-164x shown in FIG. 5 (’960 Patent, col. 6:51-54). A party may argue the term should be limited by these exemplary embodiments to circuits performing these specific functions in the manner disclosed.
  • The Term: "programmable address signal"

  • Context and Importance: This signal is the input that dictates which memory sections are to be refreshed. The definition of "programmable" is critical to determining whether an accused device, which may have a fixed partial-refresh mode, infringes.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: A party could argue that "programmable" should be given its plain and ordinary meaning, covering any signal that can be set or configured to select a subset of memory sections, even if that configuration is fixed at the factory. The claim itself does not specify how or when the signal must be programmable.
    • Evidence for a Narrower Interpretation: The specification repeatedly links this concept to a "refresh address register" that is programmed with the desired portion of memory to refresh (’960 Patent, col. 2:1-3, col. 8:3-4). This may support an argument that the term requires the presence of a specific, addressable register that can be loaded with different values to change the partial refresh configuration, rather than a hard-wired or fixed setting.

VI. Other Allegations

  • Willful Infringement: The complaint does not contain an explicit allegation of willful infringement or plead any facts related to Defendant's pre- or post-suit knowledge of the ’960 Patent. However, in the prayer for relief, Plaintiff requests that the case be declared "exceptional" under 35 U.S.C. § 285, which could lead to an award of attorney's fees (Compl. p. 4, ¶E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. An Evidentiary Question of Operation: The case currently rests on conclusory allegations. A primary threshold question is whether discovery will produce evidence that Defendant’s products technically operate in the manner required by the claims—specifically, by using control signals to selectively enable and disable the periphery array circuits of distinct memory sections to perform a partial refresh.

  2. A Definitional Question of Scope: A core legal issue will likely be the claim construction of "programmable address signal." The case may turn on whether this term is construed broadly to include any pre-set or fixed configuration for partial refresh, or narrowly to require a dynamically reconfigurable mechanism like the "refresh address register" described in the patent’s embodiments.

No probative visual evidence provided in complaint.