InnoMemory LLC v. Panasonic Corp Of North America

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory LLC (Texas)
  • Defendant: Panasonic Corporation of North America (Delaware)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:23-cv-00339, E.D. Tex., 07/20/2023
• Venue Allegations: Venue is alleged to be proper based on Defendant maintaining an established place of business within the Eastern District of Texas.
• Core Dispute: Plaintiff alleges that certain unspecified products of the Defendant infringe two patents related to power consumption and data retrieval architectures in random access memory circuits.
• Technical Context: The patents-in-suit address methods for improving power efficiency and operational flexibility in dynamic random-access memory (DRAM), a foundational technology for computers and portable electronics.
• Key Procedural History: The complaint alleges that Plaintiff provided Defendant with a notice letter on or about January 28, 2019, identifying the patents-in-suit and including a claim chart allegedly demonstrating infringement by reference to the JEDEC DDR4 industry standard.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle," issued May 29, 2001

The Invention Explained

• Problem Addressed: The patent describes a conflict in prior art memory design between power efficiency and performance (Compl. ¶9; ’046 Patent, col. 1:53-64). Memory circuits designed to retrieve multiple data words per clock cycle to accelerate "burst" operations were power-inefficient for random, single-word reads, while circuits optimized for single-word reads were slower during burst requests ('046 Patent, col. 2:1-15).
• The Patented Solution: The invention is a random access memory architecture capable of operating in different modes to balance these needs. The circuit can be configured to retrieve only a single data word from the memory array in a given clock cycle to conserve power during random access requests, or it can be configured to retrieve more than one data word to improve performance during burst requests ('046 Patent, Abstract; col. 2:45-56).
• Technical Importance: This flexible architecture sought to provide a single memory solution that could operate efficiently for both the random access patterns common in some computing tasks and the sequential burst access patterns critical for others, such as filling a processor cache ('046 Patent, col. 1:36-44).

Key Claims at a Glance

• The complaint does not identify any specific asserted claims for the ’046 Patent, instead referring to an external exhibit not provided with the complaint (Compl. ¶12, ¶14). The analysis below is based on a representative independent claim.
• Representative Independent Claim 1 includes the following essential elements:
  • A random access memory integrated circuit
  • comprising a memory array capable of storing a plurality of data words
  • and a data bus coupled to the memory array, the data bus having a width of more than one data word
  • wherein the circuit is capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations," issued June 6, 2006

The Invention Explained

• Problem Addressed: The patent's background section details the issue of power consumption in DRAM devices during standby mode (Compl. ¶10; ’960 Patent, col. 1:30-34). In battery-powered devices, not all stored data may need to be retained, yet conventional DRAMs consume power refreshing the entire memory array, which can significantly shorten battery life (’960 Patent, col. 1:40-50).
• The Patented Solution: The invention proposes a method and architecture where the memory array is divided into multiple sections. Control circuitry is provided to enable background operations, such as the power-intensive refresh process, in a selected subset of these sections while leaving the other sections inactive (’960 Patent, Abstract; col. 2:5-15).
• Technical Importance: This selective refresh capability allows for a significant reduction in standby power consumption by refreshing only the portions of memory containing critical data, a key feature for the growing market of mobile and battery-powered electronics (’960 Patent, col. 1:40-45).

Key Claims at a Glance

• The complaint does not identify any specific asserted claims for the ’960 Patent, instead referring to an external exhibit not provided with the complaint (Compl. ¶20, ¶22). The analysis below is based on a representative independent claim.
• Representative Independent Claim 1 includes the following essential elements:
  • A method for reducing power consumption during background operations in a memory array with a plurality of sections
  • comprising the step of controlling said background operations in each section in response to one or more control signals
  • wherein said control signals are generated in response to a programmable address signal
  • and said background operations can be enabled simultaneously in two or more sections independently of any other section
  • and presenting said control signals and decoded address signals to periphery array circuits of said sections

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products by name (Compl. ¶12, ¶20). It refers generally to "Exemplary Defendant Products" contained in external exhibits that were not provided with the complaint (Compl. ¶14, ¶22).

Functionality and Market Context

The complaint provides no technical description of the accused products' functionality. However, it alleges that a 2019 notice letter demonstrated infringement by referencing the JEDEC DDR4 Specification, suggesting the accused products are memory devices or modules compliant with that industry standard (Compl. ¶17). The complaint alleges that these products practice the technologies claimed by the patents-in-suit (Compl. ¶14, ¶22).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references claim-chart exhibits that were not provided, alleging that they compare the asserted claims to the accused products (Compl. ¶14, ¶22). In the absence of these charts, the infringement theory is summarized below in prose.

For the ’046 Patent, the complaint alleges that Defendant's products directly infringe by practicing the claimed technology for flexibly reading data words from memory (Compl. ¶12-14). The infringement theory appears to rely on the functionality of products compliant with the JEDEC DDR4 standard, which supports various burst-read modes that deliver sequential data over multiple clock cycles (Compl. ¶17).

For the ’960 Patent, the complaint alleges that Defendant's products directly infringe by practicing the claimed technology for reducing power consumption during refresh operations (Compl. ¶20-22). The infringement theory likely targets power-saving features in modern DRAM, such as the Partial Array Self-Refresh (PASR) modes defined in standards like DDR4, which allow a device to refresh only a portion of its memory array.

Identified Points of Contention

• ’046 Patent - Technical Question: An evidentiary question may arise as to whether the standard operation of DDR4 memory, which often involves an internal prefetch of multiple data words followed by sequential output over several clock cycles, meets the claim limitation of "retrieving a first data word...in a first clock cycle and a second data word...in a second clock cycle." The dispute may focus on whether "retrieving" requires distinct memory array accesses in each cycle.
• ’960 Patent - Scope Question: A central claim construction dispute may concern the scope of the term "programmable address signal." The analysis may question whether standard DDR4 mechanisms for enabling partial refresh modes, typically set via a mode register, constitute a "programmable address signal" as contemplated by the patent.

V. Key Claim Terms for Construction

The complaint offers no basis for claim construction analysis. The following analysis is based on representative independent claims from the patents-in-suit.

’046 Patent, Representative Claim 1

• The Term: "retrieving... from the memory array"
• Context and Importance: Practitioners may focus on this term because the definition is critical to determining when infringement occurs in a modern DRAM architecture. The dispute will likely center on whether "retrieving from the memory array" refers to the initial internal read from the physical memory cells into a buffer, or the subsequent output of that data from the buffer onto the data bus over one or more clock cycles.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language requires retrieving a first word "in a first clock cycle" and a second word "in a second clock cycle" without specifying that the physical access to the memory cells must occur in those distinct cycles (’046 Patent, col. 100:10-15). This could support a reading where outputting buffered data constitutes "retrieving."
  • Evidence for a Narrower Interpretation: The summary of the invention distinguishes between retrieving one word from the array versus more than one word from the array in a single cycle, tying the "retrieval" act directly to the memory array itself, not an intermediate buffer (’046 Patent, col. 2:45-56).

’960 Patent, Representative Claim 1

• The Term: "programmable address signal"
• Context and Importance: Practitioners may focus on this term because its construction will determine whether standard industry mechanisms for partial refresh fall within the claim scope. The case may turn on whether this term requires a specific type of signal or programming mechanism.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim requires the control signals to be generated "in response to" the programmable address signal, suggesting an indirect link (’960 Patent, col. 8:50-55). This could support an interpretation that includes settings in a general-purpose mode register that are derived from an address command.
  • Evidence for a Narrower Interpretation: An embodiment described in the specification shows a dedicated "refresh address register 18" that is programmed with "the portion of the memory array 26 to be refreshed" and "controls the higher order bits of the refresh addresses" (’960 Patent, col. 2:1-4). This could support a narrower construction requiring a dedicated register that directly controls address bits for section selection.

VI. Other Allegations

Indirect Infringement

The complaint alleges inducement of infringement based on Defendant’s distribution of "product literature and website materials" that allegedly instruct users on how to operate the accused products in an infringing manner (Compl. ¶18).

Willful Infringement

The complaint alleges willful infringement based on pre-suit knowledge. It claims that Defendant has had actual knowledge of its infringement since at least January 28, 2019, when it allegedly received a notice letter identifying the patents-in-suit and providing an infringement analysis (Compl. ¶17, ¶25).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A threshold issue may be one of pleading sufficiency: given the complaint's reliance on external, non-public exhibits and its failure to identify any specific accused products or asserted claims, a key question is whether it provides sufficient factual detail to state a plausible claim for relief under prevailing federal pleading standards.
2. A core issue for the ’960 patent will be one of definitional scope: can the term "programmable address signal," which the patent illustrates with a dedicated refresh address register, be construed broadly enough to read on the industry-standard mode register settings used to configure partial self-refresh operations in DDR4-compliant memory?
3. A key evidentiary question for the ’046 patent will be one of technical mapping: what evidence can Plaintiff produce to demonstrate that the internal operations of the accused products—specifically, how they handle prefetching and burst reads—satisfy the sequential "retrieving...from the memory array" limitations recited in the patent’s claims?