InnoMemory LLC v. ASUSTeK Computer Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory LLC (Texas)
  • Defendant: Asustek Computer Inc. (Taiwan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:23-cv-00340, E.D. Tex., 07/21/2023
• Venue Allegations: Plaintiff alleges venue is proper because Defendant, a foreign corporation, has committed acts of patent infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant’s products incorporating certain types of random access memory infringe patents related to memory architecture, data retrieval methods, and power-saving refresh operations.
• Technical Context: The technology concerns improvements in the performance and power efficiency of dynamic random-access memory (DRAM), a fundamental component in computers and electronic devices.
• Key Procedural History: The complaint alleges that Plaintiff provided Defendant with notice of infringement for both patents-in-suit via a letter on or about February 1, 2019, more than four years prior to filing the lawsuit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle"

• Patent Identification: U.S. Patent No. 6,240,046, "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle," issued May 29, 2001.

The Invention Explained

• Problem Addressed: The patent’s background section describes a trade-off in prior art memory devices between performance and power consumption, particularly for portable computing systems ('046 Patent, col. 2:1-15). Some memory circuits that retrieved multiple data words per cycle wasted power if only one word was needed, while circuits retrieving only one word at a time could be less efficient for sequential "burst" read operations ('046 Patent, col. 2:1-12).
• The Patented Solution: The invention discloses a random access memory architecture capable of operating in two different modes to balance these needs. The memory can be configured to retrieve only a single data word from the memory array in one clock cycle to conserve power during random access requests. Alternatively, it can be configured to retrieve more than one data word in a single clock cycle to improve efficiency during burst requests, where multiple sequential data words are needed ('046 Patent, Abstract; col. 2:45-56). A flip-flop is described that can be set to control which mode the circuit uses, potentially switching based on the nature of the read requests ('046 Patent, col. 2:45-68).
• Technical Importance: This flexible data retrieval method aimed to deliver both the high performance required by increasingly powerful processors and the low power consumption critical for the growing market of battery-operated portable devices ('046 Patent, col. 1:50-63).

Key Claims at a Glance

• The complaint does not identify specific asserted claims, instead referring to "Exemplary '046 Patent Claims" detailed in an unattached exhibit (Compl. ¶12, ¶14).

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

• Patent Identification: U.S. Patent No. 7,057,960, "Method and architecture for reducing the power consumption for memory devices in refresh operations," issued June 06, 2006.

The Invention Explained

• Problem Addressed: The patent addresses power consumption in DRAMs during standby or power-down modes ('960 Patent, col. 1:35-41). Conventional DRAMs refresh all memory cells periodically to retain data, which consumes significant power even when the device is idle. For applications like portable telephones where only a portion of the memory data needs to be retained, refreshing the entire memory array is inefficient ('960 Patent, col. 1:41-56).
• The Patented Solution: The invention proposes dividing the memory array into multiple sections (e.g., quadrants) and providing a mechanism to control background operations, such as refresh, on a section-by-section basis ('960 Patent, Abstract; col. 2:37-49). By activating the periphery array circuits for only the sections that require data retention and leaving the circuits for other sections inactive, the memory device can significantly reduce its standby power consumption ('960 Patent, col. 2:41-49).
• Technical Importance: This selective refresh architecture was designed to lower power consumption in battery-powered devices, directly addressing a critical need for the mobile electronics market by extending standby time ('960 Patent, col. 1:29-34).

Key Claims at a Glance

• The complaint does not identify specific asserted claims, instead referring to "Exemplary '960 Patent Claims" detailed in an unattached exhibit (Compl. ¶20, ¶22).

III. The Accused Instrumentality

• Product Identification: The complaint does not name specific accused products. It refers generally to "Exemplary Defendant Products" that are identified in claim charts incorporated as Exhibits 3 and 4, which were not filed with the complaint (Compl. ¶12, ¶20).
• Functionality and Market Context: The complaint does not provide sufficient detail for analysis of the accused products' specific functionality. It alleges that the products "practice the technology claimed" by the patents-in-suit (Compl. ¶14, ¶22). The complaint further alleges on information and belief that "numerous other devices" also infringe (Compl. ¶12, ¶20).

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits that were not provided. Therefore, the infringement allegations are summarized below in prose.

• ’046 Patent Infringement Allegations: The complaint alleges that Defendant's products directly infringe one or more claims of the ’046 Patent (Compl. ¶12). The core of the infringement theory appears to rely on an assertion that Defendant's products comply with the JEDEC DDR4 Specification, which the complaint alleges demonstrates infringement (Compl. ¶17). The complaint asserts that the charts in Exhibit 3 show that the "Exemplary Defendant Products" satisfy all elements of the asserted claims (Compl. ¶14).
• ’960 Patent Infringement Allegations: The complaint alleges that Defendant's products directly infringe one or more claims of the ’960 Patent (Compl. ¶20). The narrative theory is that the charts provided in Exhibit 4 compare the asserted claims to the accused products and demonstrate that the products practice the claimed technology (Compl. ¶22).

No probative visual evidence provided in complaint.

V. Key Claim Terms for Construction

As the complaint does not specify the asserted claims or provide the referenced claim chart exhibits, there is no basis for identifying key claim terms for construction.

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement of infringement for both patents. It asserts that Defendant distributes "product literature and website materials inducing end users and others to use its products in the customary and intended manner that infringed" the patents-in-suit (Compl. ¶18, ¶26).
• Willful Infringement: The complaint alleges willful infringement of both patents based on Defendant’s alleged actual knowledge. This knowledge is claimed to stem from a notice letter sent on or about February 1, 2019, which allegedly identified the patents-in-suit, provided claim charts, and, for the '046 Patent, referenced the JEDEC DDR4 Specification (Compl. ¶17, ¶25). Plaintiff alleges that Defendant’s infringement continued despite this notice (Compl. ¶18, ¶26).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central evidentiary issue will be one of specificity and proof: because the complaint's infringement allegations are made entirely by reference to unattached exhibits, a key question is whether the forthcoming factual details will be sufficient to demonstrate that Defendant's products—which are themselves not yet specifically identified—actually perform every limitation of the asserted claims.
• For the '046 Patent, the case raises a question of standards-essentiality and claim scope: the complaint ties infringement to the JEDEC DDR4 Specification. This suggests a core dispute will be whether compliance with that industry standard necessarily results in infringement, a determination that will heavily influence both claim construction and the scope of accused products.
• The willfulness claim will likely turn on the adequacy of pre-suit notice: given the more than four-year gap between the alleged notice letter and the filing of the suit, a critical question will be whether the 2019 letter provided Defendant with knowledge of infringement that was specific and clear enough to support a finding of egregious or willful misconduct for its subsequent commercial activity.