InnoMemory LLC v. Acer Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory LLC (Texas)
  • Defendant: Acer Inc. (Taiwan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:23-cv-00341, E.D. Tex., 07/21/2023
• Venue Allegations: Plaintiff alleges venue is proper because Defendant, a foreign corporation, has committed acts of infringement within the district, causing harm to the Plaintiff.
• Core Dispute: Plaintiff alleges that Defendant’s products incorporating certain memory devices infringe patents related to power-saving techniques and efficient data access in random access memory.
• Technical Context: The technology at issue involves methods for reducing power consumption in Dynamic Random Access Memory (DRAM), a critical component in nearly all modern computing devices.
• Key Procedural History: Plaintiff alleges it provided Defendant with pre-suit notice of infringement on or about February 1, 2019, including a claim chart for one of the patents-in-suit that referenced the JEDEC DDR4 memory standard.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046, "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle," issued May 29, 2001 (’046 Patent)

• The Invention Explained:
  • Problem Addressed: The patent’s background section describes a need for memory devices with lower power consumption, particularly for portable computing systems. It notes that some prior art memories retrieve multiple data words in a single cycle even when only one is requested, which wastes power by performing unnecessary memory array activity (Compl. ¶9; ’046 Patent, col. 2:1-15).
  • The Patented Solution: The invention proposes a memory circuit that can switch between two operational modes. In a first mode, it retrieves only one data word in a clock cycle, conserving power during random read operations. In a second mode, it retrieves more than one data word, which can be more efficient for sequential "burst" read operations by reducing the total number of memory array accesses. The selection between these modes is controlled by a "flip-flop" that stores the operational state (’046 Patent, Abstract; col. 2:45-49).
  • Technical Importance: This adaptive approach allows the memory to balance power consumption and performance based on the specific type of data access required, a key consideration for battery-powered electronics (’046 Patent, col. 2:11-15).
• Key Claims at a Glance:
  The complaint asserts infringement of "one or more claims" of the ’046 Patent but does not specify them, instead referring to an unattached exhibit (Compl. ¶12, ¶14). Independent claim 5 is representative of the invention’s dual-mode power-saving feature.
  • Independent Claim 5: An apparatus claim for a random access memory integrated circuit comprising:
    • a flip-flop having a first state and a second state,
    • wherein in the first state one data word of the plurality of data words is retrieved from the memory array in a single clock cycle
    • and in the second state more than one data word of the plurality of data words are retrieved from the memory array in the single clock cycle.

U.S. Patent No. 7,057,960, "Method and architecture for reducing the power consumption for memory devices in refresh operations," issued June 6, 2006 (’960 Patent)

• The Invention Explained:
  • Problem Addressed: The patent’s background section explains that conventional dynamic memory devices consume significant power in standby mode because they must periodically refresh all memory cells to prevent data loss. A key inefficiency is that during a refresh operation, the support circuitry ("periphery array circuits") for all sections of the memory array is activated, even when only a portion of the array requires data retention and refreshing (’960 Patent, col. 1:36-48, col. 2:23-29).
  • The Patented Solution: The invention discloses an architecture that reduces standby power consumption by selectively controlling background operations, such as refresh, on a section-by-section basis. It uses specific control signals to activate the periphery array circuits only for the memory sections being refreshed, while leaving the circuitry for other sections inactive. This is illustrated in Figure 3, where control signals REF0-REF3 correspond to four separate memory quadrants (’960 Patent, Abstract; Fig. 3).
  • Technical Importance: This method provides more granular control over the power-intensive refresh process, which is critical for extending the battery life of portable electronics that spend significant time in standby mode (’960 Patent, col. 1:31-35).
• Key Claims at a Glance:
  The complaint asserts infringement of "one or more claims" of the ’960 Patent without specification, referring to an unattached exhibit (Compl. ¶20, ¶22). Independent claim 10 is a representative apparatus claim.
  • Independent Claim 10: An apparatus claim for a memory device comprising:
    • a memory array comprising a plurality of sections, each with memory cells and "periphery array circuitry"; and
    • a control circuit configured to present one or more control signals and decoded address signals to the periphery array circuitry;
    • wherein the control signals are generated in response to a programmable address signal, and a background operation (e.g., refresh) in each section is controlled by said control signals;
    • such that the background operation can be enabled simultaneously in two or more sections independently of any other section.

III. The Accused Instrumentality

• Product Identification: The complaint identifies "Exemplary Defendant Products" but refers to unattached exhibits (Compl. ¶¶12, 20). It further alleges that Acer products incorporating memory compliant with the "JEDEC DDR4 Specification" infringe the ’046 Patent (Compl. ¶17).
• Functionality and Market Context: The complaint does not provide specific technical details about the accused products' operation. The infringement theory for the ’046 Patent appears to be grounded in the functionality mandated by the DDR4 industry standard, which governs the behavior of synchronous dynamic random-access memory used in a vast range of computing products (Compl. ¶17). For the ’960 Patent, the complaint alleges infringement by Acer products without specifying an operative standard or technical mechanism (Compl. ¶20).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint incorporates claim charts by reference in Exhibits 3 and 4, which were not filed with the complaint (Compl. ¶¶15, 23). The narrative infringement theories are summarized below.

’046 Patent Infringement Allegations

The complaint’s narrative theory suggests infringement by products that comply with the JEDEC DDR4 Specification (Compl. ¶17). DDR4 memory supports both single-access and burst-mode reads, which require the memory to be capable of retrieving either a single data word or multiple sequential data words. This functionality aligns with the dual-mode retrieval capability described in the ’046 Patent.

• Identified Points of Contention:
  • Scope Questions: A central question may be whether mere compliance with the DDR4 standard necessitates the presence of every element of the asserted claims. For example, does the standard mandate a structure that meets the claim limitation of a "flip-flop" for controlling the retrieval mode, or can compliance be achieved through other means that fall outside the claim’s scope?

’960 Patent Infringement Allegations

The complaint alleges that accused products practice the patented technology for reducing power consumption during refresh operations (Compl. ¶20). The narrative does not provide a specific technical basis for this allegation, such as citing a particular industry standard or operational mode of the accused products.

• Identified Points of Contention:
  • Technical Questions: The infringement analysis will likely depend on detailed evidence of the accused memory devices' internal architecture. A key question will be what evidence the Plaintiff provides to show that the accused products implement the specific function of selectively enabling and disabling "periphery array circuitry" for individual memory sections during refresh, as required by the claims.

V. Key Claim Terms for Construction

’046 Patent: "flip-flop" (from Claim 5)

• Context and Importance: This term recites a specific circuit structure. The dispute may turn on whether the mechanism used in the accused DDR4 memory to switch between single-word and multi-word read modes constitutes a "flip-flop" as understood in the patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent does not provide a specific definition, describing the element functionally as being set to a first or second state to control the retrieval mode (’046 Patent, col. 2:45-49). A party may argue this covers any bistable circuit element that stores a state bit for this purpose, including a bit within a general-purpose mode register.
  • Evidence for a Narrower Interpretation: A party may argue that the term should be limited to its conventional structural meaning in digital logic design, potentially excluding other state-storage mechanisms like a software-accessible register bit that is not part of a dedicated, hardware-driven state machine in the manner of a traditional flip-flop.

’960 Patent: "periphery array circuitry" (from Claim 10)

• Context and Importance: The claim requires this circuitry to be controlled on a per-section basis to save power. The definition of this term is critical to determining whether the power-saving modes in accused devices operate in an infringing manner.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification suggests this term encompasses the various support circuits for a memory section. An exemplary list includes "sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" (’960 Patent, col. 5:53-57).
  • Evidence for a Narrower Interpretation: A party could argue the term is limited to architectures where all the listed circuit types are collectively and selectively disabled as shown in the patent's specific embodiments (e.g., ’960 Patent, Fig. 5). If an accused device’s low-power mode disables only a subset of these circuits, it might be argued to fall outside the claim scope.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for both patents, asserting that Defendant’s "product literature and website materials" instruct end users to operate the accused products in an infringing manner (Compl. ¶¶18, 26).
• Willful Infringement: The complaint alleges willful infringement based on Defendant's alleged pre-suit knowledge of the patents-in-suit. This knowledge is purportedly established by a notice letter and claim chart sent to Acer on or about February 1, 2019, more than four years before the complaint was filed (Compl. ¶¶17-18, 25-26).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue for the ’046 Patent will be one of infringement by standard: can Plaintiff prove that compliance with the JEDEC DDR4 standard necessarily requires practicing every limitation of the asserted claims, including the "flip-flop," or must it additionally show a specific, infringing design choice made by the manufacturer of the memory in Defendant's products?
• A key evidentiary question for the ’960 Patent will be one of architectural proof: what technical evidence, likely from reverse engineering or internal documentation, will Plaintiff present to demonstrate that the commodity memory components in Acer's products contain the specific internal architecture required by the claims, namely the independent control of "periphery array circuitry" for distinct memory sections during refresh?