DCT

2:23-cv-00429

Deepwell IP LLC v. MediaTek Inc

I. Executive Summary and Procedural Information

Parties & Counsel:
- Plaintiff: Deepwell IP LLC (Texas)
- Defendant: MediaTek Inc. (Taiwan)
- Plaintiff’s Counsel: Fabricant LLP; Truelove Law Firm, PLLC
Case Identification: 2:23-cv-00429, E.D. Tex., 09/19/2023
Venue Allegations: Venue is alleged to be proper because the defendant is a foreign corporation, which may be sued in any judicial district, and because the defendant has allegedly committed acts of infringement and conducts business in the Eastern District of Texas.
Core Dispute: Plaintiff alleges that Defendant’s System-on-Chip (SoC) products, which feature ARM cores, infringe four U.S. patents related to integrated circuit power management, performance optimization, and fabrication techniques.
Technical Context: The technologies at issue address fundamental challenges in modern semiconductor design, including managing processor performance, power consumption, and the physical layout of circuits on a chip.
Key Procedural History: The complaint notes the technology underlying the patents was developed by Transmeta Corporation. U.S. Patent No. RE44,025 is a reissue of U.S. Patent No. 7,080,341. The complaint does not mention any prior litigation or administrative proceedings involving these patents.

Case Timeline

Date	Event
2002-12-31	Priority Date ('664 & '730 Patents)
2003-08-21	Priority Date ('851 Patent)
2003-09-09	Priority Date ('025 Patent)
2006-12-12	Issue Date (U.S. Patent No. 7,149,851)
2010-01-12	Issue Date (U.S. Patent No. 7,645,664)
2013-02-19	Issue Date (U.S. Patent No. RE44,025)
2013-04-09	Issue Date (U.S. Patent No. 8,415,730)
2022	The Motorola Edge 2022, incorporating an accused SoC, is sold in the U.S.
2023-09-19	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,149,851 - "Method And System For Conservatively Managing Store Capacity Available To A Processor Issuing Stores"

Issued: December 12, 2006.
The Invention Explained:
- Problem Addressed: The patent describes a latency issue in high-performance processors where a processor may issue a "store" (a data write instruction) without immediately knowing if the destination "store container" (e.g., a buffer or cache) is full, which can lead to data-corrupting overflow errors (’851 Patent, col. 1:12-29).
- The Patented Solution: The invention proposes a "counter mechanism" that maintains a conservative estimate of the used capacity of the store container. The counter increments when a store is issued and decrements as stores are processed. If the counter reaches a predetermined threshold, indicating the container is likely near full, it triggers a response to pause the processor and determine the actual available capacity, thereby preventing an overflow before it can occur (’851 Patent, Abstract; col. 2:36-54).
- Technical Importance: This method allows a processor to operate at high speed with asynchronous memory operations while providing a safeguard to maintain data integrity.
Key Claims at a Glance:
- The complaint asserts at least independent method claim 35 (Compl. ¶17).
- Claim 35 requires the following steps:
  - incrementing a counter mechanism when a store is issued;
  - decrementing the counter mechanism for each decrementing condition occurring relative to store capacity; and
  - when the counter's value equals a predetermined value, executing a response to determine if store capacity has been exceeded.
- The complaint reserves the right to assert other claims from the patent (’851 Patent, col. 11:35-44; Compl. ¶16).

U.S. Patent No. 7,645,664 - "Layout Pattern For Deep Well Region To Facilitate Routing Body-bias Voltage"

Issued: January 12, 2010.
The Invention Explained:
- Problem Addressed: Applying a "body-bias" voltage to transistors can enhance performance, but routing this voltage traditionally requires creating an additional metal layer on the surface of the semiconductor chip, where physical space is extremely limited and valuable (’664 Patent, col. 1:34-53).
- The Patented Solution: The invention describes using a sub-surface "deep N-well" to create a conductive grid for routing the body-bias voltage beneath the active transistor layers. This frees up the valuable surface area for other connections. The patent details specific layout patterns, such as a diagonal mesh, for these deep wells to provide effective voltage distribution without interfering with other circuit elements (’664 Patent, Abstract; col. 2:55-62; FIG. 5A).
- Technical Importance: This technique enables chip designers to gain the performance advantages of body-biasing without consuming premium surface real estate, facilitating denser and more efficient integrated circuits.
Key Claims at a Glance:
- The complaint asserts at least independent method claim 1 (Compl. ¶34).
- Claim 1 requires the steps of:
  - forming a plurality of well regions of a first conductivity to receive a voltage;
  - forming a sub-surface structure of the same conductivity that is coupled to the well regions and has a greater depth; and
  - forming a contact coupled to the sub-surface structure to receive the voltage and enable it to be routed to the well regions.
- The complaint reserves the right to assert other claims from the patent (’664 Patent, col. 11:61-12:7; Compl. ¶33).

U.S. Patent No. 8,415,730 - "Selective Coupling Of Voltage Feeds For Body Bias Voltage In An Integrated Circuit Device"

Issued: April 9, 2013.
Technology Synopsis: This patent discloses a flexible body-biasing mechanism for integrated circuits. The invention provides a resistive structure that automatically couples body biasing wells to an internal power supply voltage (e.g., Vdd) in the absence of an external body bias voltage, but couples them to an externally-supplied voltage if one is provided via a dedicated pin. This allows a single chip design to support both configurations (’730 Patent, Abstract; Compl. ¶8).
Asserted Claims: At least method claim 16 (Compl. ¶47).
Accused Features: The complaint alleges that the accused SoCs contain a body bias distribution circuit and transistors that couple a power rail to this distribution network, thereby practicing the claimed method (Compl. ¶¶48-49).

U.S. Patent No. RE44,025 - "Apparatus And Method For Integrated Circuit Power Management"

Issued: February 19, 2013.
Technology Synopsis: This patent describes a power management technique using "power islands," which are logic circuits that can be powered on or off independently. The invention places the power gating circuits—the transistors that act as switches—within the Input/Output (I/O) ring of the chip instead of the core logic area. This method is used to control power to different power islands, including providing different voltage levels, which frees up valuable core real estate and simplifies the design process (’025 Patent, Abstract; Compl. ¶9).
Asserted Claims: At least method claim 35 (Compl. ¶58).
Accused Features: The complaint alleges the accused SoCs utilize power islands and power gating transistors to control power to logic circuits, such as voltage and sensing circuits (Compl. ¶¶59-60).

III. The Accused Instrumentality

Product Identification

The complaint names "all MediaTek SoCs with ARM cores" as the accused instrumentalities, specifically identifying the MT8186 and Dimensity 1050 SoCs (Compl. ¶12). Downstream products incorporating these SoCs, such as the Lenovo Chromebook and Motorola Edge 2022, are also mentioned (Compl. ¶12).

Functionality and Market Context

The Accused Products are Systems-on-Chip that form the central processing unit for consumer electronic devices (Compl. ¶¶12, 18). According to the complaint, their functionality includes a "store buffer" to manage write requests, a "Performance Monitoring Unit (PMU)" with event counters to monitor operations, a "body bias distribution circuit" to provide voltage, and a "power island" architecture for power management (Compl. ¶¶18, 19, 48, 59). A marketing infographic for the MediaTek Kompanio 520, which the complaint identifies as the MT8186, is provided as evidence of a "Store buffer" (Compl. p. 6). The complaint alleges these products are sold and incorporated into devices sold in the United States (Compl. ¶12).

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,149,851 Infringement Allegations

Claim Element (from Independent Claim 35)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a method of conservatively managing a store capacity of a store container receiving issued stores from a processor having a counter mechanism...	The accused SoCs allegedly contain a processor with a store buffer (store container) and a Performance Monitoring Unit (PMU) that functions as a counter mechanism.	¶18, ¶19	col. 2:36-40
incrementing said counter mechanism when a store is issued;	The PMU's counters are allegedly incremented upon a "Data Write architecturally executed" event, which is equated with an issued store. A table from ARM documentation shows this event is countable.	¶22	col. 3:13-15
decrementing said counter mechanism for each decrementing condition occurring relative to said store capacity;	The complaint alleges the PMU includes non-monotonic monitors that can decrement when a resource is deallocated, such as when a store buffer entry is drained or a writeback occurs.	¶24	col. 3:16-24
when a value of said counter mechanism equals a predetermined value, executing a response to determine whether said store capacity has been exceeded.	The PMU architecture allegedly includes a mechanism to "generate an interrupt when a counter reaches a threshold value," which is equated with executing a response at a predetermined value. A document snippet illustrates this capability.	¶25	col. 2:44-54

Identified Points of Contention:
- Scope Questions: A primary question may be whether the accused "Performance Monitoring Unit (PMU)," a general-purpose diagnostic and profiling tool, constitutes the specific "counter mechanism for conservatively managing a store capacity" as contemplated by the patent. The patent's specification and figures appear to describe a dedicated hardware counter integrated with the store buffer logic for the sole purpose of overflow prevention (’851 Patent, FIG. 1), whereas the PMU is a more general, software-accessible monitoring system (Compl. ¶19).
- Technical Questions: The complaint alleges that the PMU's event counters are used to perform the claimed method. However, one of the complaint's own exhibits states that in the CoreSight PMU Architecture, "event counters are monotonically increasing" (Compl. p. 14). This raises the question of how a monotonically increasing counter can perform the claimed step of "decrementing said counter mechanism."

U.S. Patent No. 7,645,664 Infringement Allegations

The complaint does not provide sufficient detail to map specific features of the Accused Products to the elements of claim 1. The allegations in paragraphs 36-38 are conclusory and largely recite the claim language without reference to technical evidence or specific product functionality.

Identified Points of Contention:
- Evidentiary Questions: The core of the dispute will likely be evidentiary. Claim 1 is a method claim reciting steps of "forming" semiconductor structures. The complaint accuses MediaTek of infringement by, among other things, selling and using the finished SoCs. This raises the question of whether selling a finished product can constitute infringement of a claim directed to a method of manufacture. The complaint does not provide specific factual allegations or visual evidence demonstrating that the accused SoCs contain the claimed sub-surface routing structures. For example, a provided circuit diagram for the '730 patent shows a hybrid power switch but does not depict the sub-surface layout central to the '664 patent's claims (Compl. p. 20).

V. Key Claim Terms for Construction

For the ’851 Patent:

The Term: "counter mechanism"
Context and Importance: The infringement theory depends on equating the accused SoCs' general-purpose Performance Monitoring Unit (PMU) with the claimed "counter mechanism." The construction of this term will be critical to determining whether there is a literal match. Practitioners may focus on this term because the patent appears to describe a dedicated hardware system, while the accused feature is a flexible, software-driven diagnostic tool.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the mechanism in general terms as being "incremented or decremented based on the occurrence of particular events" and receiving "several input signals," language which could potentially read on a versatile tool like a PMU (’851 Patent, col. 2:32-36).
- Evidence for a Narrower Interpretation: The patent consistently frames the invention as a way to "conservatively manage" store capacity to "avoid the overflow condition" (’851 Patent, col. 2:37-38). Figure 1 depicts a single, dedicated "COUNTER MECHANISM 20" block, which may suggest a specific, integrated hardware component rather than a general-purpose monitoring unit.

For the ’664 Patent:

The Term: "forming"
Context and Importance: Claim 1 is a method claim, and the dispute will likely center on what actions constitute "forming" the claimed structures. The infringement allegation rests on acts of making, using, and selling the accused SoCs. The definition of "forming" will determine whether selling a completed chip, or having it manufactured by a third party, constitutes direct infringement of the fabrication method.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The complaint does not present intrinsic evidence for a broad interpretation that would cover post-fabrication activities. A plaintiff could argue that "making" the device inherently includes the "forming" steps.
- Evidence for a Narrower Interpretation: The claim language ("forming a plurality of well regions," "forming a sub-surface structure") and the specification's focus on physical layout patterns for semiconductor manufacturing strongly suggest that "forming" refers to the actual fabrication steps performed in a foundry (’664 Patent, col. 2:34-53).

VI. Other Allegations

Indirect Infringement: The complaint alleges induced infringement for all four patents. The allegations are based on MediaTek providing "instruction manuals, websites, promotional materials, advertisements, and other information" to customers and end-users, which allegedly instruct them on how to use the Accused Products in an infringing manner (Compl. ¶¶ 26-28, 39-41, 50-52, 61-63).
Willful Infringement: Willfulness is alleged based on knowledge of the patents "by no later than the date of this Complaint" (e.g., Compl. ¶27). The complaint also pleads willful blindness as an alternative theory for inducement (e.g., Compl. ¶28). There are no allegations of pre-suit knowledge or notice.

VII. Analyst’s Conclusion: Key Questions for the Case

Functional Equivalence vs. Mismatch: A primary issue for the ’851 patent will be one of functional scope: does the accused, general-purpose Performance Monitoring Unit (PMU) operate as the dedicated, closed-loop "counter mechanism for conservatively managing store capacity" required by the claim, or is there a fundamental mismatch in its technical operation and purpose?
Infringing Act vs. Claim Type: For the method claims, particularly in the ’664 patent, a key legal question will be one of infringing conduct: can the acts of selling and distributing finished semiconductor chips constitute direct infringement of claims that recite steps of "forming" physical structures during manufacturing?
Evidentiary Sufficiency: Across all asserted patents, a central challenge will be one of evidentiary support. The complaint's allegations, particularly for the ’664, ’730, and ’025 patents, will need to be substantiated with technical evidence that goes beyond the provided high-level marketing materials and conclusory statements to demonstrate how the accused devices specifically practice each claimed element.