Netlist Inc v. Micron Technology Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Netlist, Inc. (Delaware)
  • Defendant: Micron Technology, Inc. (Delaware), Micron Semiconductor Products, Inc. (Idaho), and Micron Technology Texas LLC (Idaho)
  • Plaintiff’s Counsel: McKool Smith, P.C.
• Case Identification: 2:23-cv-00628, E.D. Tex., 02/07/2024
• Venue Allegations: Plaintiff alleges venue is proper because Defendants have committed acts of patent infringement in the district and maintain regular and established places of business in the district.
• Core Dispute: Plaintiff seeks a declaratory judgment that its assertions of patent infringement against Defendant's memory products were brought in good faith, in response to Defendant filing retaliatory bad faith litigation in Idaho state court.
• Technical Context: The dispute centers on high-performance computer memory modules, such as DDR4 and DDR5 DIMMs, which are fundamental components in servers, data centers, and personal computers.
• Key Procedural History: The complaint details a complex procedural history involving multiple infringement suits filed by Netlist against Micron in Texas. In response, Micron filed actions in Idaho state court alleging Netlist's patent assertions were made in "bad faith" under an Idaho statute. This declaratory judgment action by Netlist is a direct response, seeking a federal court ruling that its original infringement suits were not brought in bad faith. The complaint also notes that a jury found some of the asserted patents not invalid in separate litigation against Samsung and that Inter Partes Review (IPR) challenges are pending.

Case Timeline

Date	Event
2005-07-01	Priority Date for ’417 and ’215 Patents
2007-06-01	Priority Date for ’918 and ’054 Patents
2007-09-27	Priority Date for ’912 Patent
2009-11-17	’912 Patent Issued
2010-11-03	Priority Date for ’060 and ’160 Patents
2012-07-27	Priority Date for ’506 Patent
2013-08-20	Priority Date for ’339 Patent
2014-07-22	’060 Patent Issued
2015-02-01	Netlist allegedly presented ’506 and ’339 technologies to Micron
2015-04-01	Netlist allegedly presented ’918, ’054, ’060, and ’160 technologies to Micron
2016-08-19	’160 Patent Issued
2018-01-02	’215 Patent Issued
2020-12-08	’506 Patent Issued
2021-03-16	’339 Patent Issued
2021-04-28	Netlist filed infringement suits against Micron, providing actual notice of the patents
2021-05-25	’918 Patent Issued
2021-08-17	’417 Patent Issued
2022-01-25	’054 Patent Issued
2023-12-11	Micron filed retaliatory lawsuit in Idaho state court
2024-02-07	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,860,506 - “Memory Module With Timing-Controlled Data Buffering”

The Invention Explained

• Problem Addressed: The patent describes that in high-density, multi-rank memory modules, the unequal wire lengths to different memory components can cause timing variations in control and data signals, compromising system performance, especially at high operating speeds (’506 Patent, col. 2:18-34).
• The Patented Solution: The invention proposes a memory module with data buffers positioned between the memory controller bus and the memory devices. These buffers include delay circuits that can adjust the timing of read data and read strobes based on control signals, effectively compensating for timing variations and ensuring proper data alignment when reading from different ranks of memory devices (’506 Patent, col. 3:9-19; Fig. 1).
• Technical Importance: This approach allows for higher memory density and faster operating speeds by actively managing signal timing on the module itself, rather than relying solely on the memory controller's leveling mechanisms (’506 Patent, col. 2:26-34).

Key Claims at a Glance

• The complaint’s allegations appear to read on independent claim 1.
• Independent Claim 1 Elements:
  • A memory module operable in a computer system to communicate with a memory controller.
  • A module board with edge connections for a memory bus.
  • A module control device on the board to receive input C/A signals and output registered C/A signals and module control signals.
  • Memory devices arranged in multiple ranks on the board, where a selected rank performs a memory read operation, outputting read data and read strobes.
  • A first memory device in the selected rank outputs at least a first section of read data and a first read strobe.
  • Data buffers on the board coupled between the edge connections and memory devices.
  • A first data buffer coupled to the first memory device that is configurable to:
    • delay the first read strobe by a first predetermined amount to generate a first delayed read strobe;
    • sample the first section of the read data using the first delayed read strobe; and
    • transmit the first section of the read data to a first section of the data bus.
  • The first predetermined amount is determined based at least on signals received by the first data buffer during one or more previous operations.
• The complaint does not explicitly reserve the right to assert other claims, but this is standard practice.

U.S. Patent No. 10,949,339 - “Memory Module With Controlled Byte-Wise Buffers”

The Invention Explained

• Problem Addressed: The patent background explains that as memory density increases, physical limitations can dictate design parameters, and attributes like power dissipation and operational speed can be detrimentally affected (’339 Patent, col. 2:5-12).
• The Patented Solution: The invention describes a memory module with a plurality of "byte-wise buffers." These buffers are controlled by a module controller to actively drive byte-wise sections of data between the memory controller and the selected memory rank during a read or write operation. This architecture allows for more granular control over data flow across the module (’339 Patent, col. 2:48-61; Fig. 5).
• Technical Importance: By managing data in byte-wise sections, the module can potentially improve signal integrity and performance for high-width data buses, which are common in server memory (’339 Patent, col. 2:48-55).

Key Claims at a Glance

• The complaint’s allegations appear to read on independent claim 1.
• Independent Claim 1 Elements:
  • An N-bit-wide memory module mountable in a computer system.
  • A printed circuit board (PCB) with an edge connector.
  • Double data rate dynamic random access memory (DDR DRAM) devices coupled to the PCB and arranged in multiple N-bit-wide ranks.
  • A module controller coupled to the PCB and operatively coupled to the DDR DRAM devices, configurable to receive input address and control signals for a memory write operation and output registered signals to cause a first rank to perform the write operation.
  • The module controller is further configurable to output module control signals.
  • A plurality of byte-wise buffers coupled to the PCB and configured to receive the module control signals.
  • Each byte-wise buffer has a first side coupled to data signal lines and a second side coupled to DDR DRAM devices, with a byte-wise data path between them.
  • The byte-wise data path includes first tristate buffers and logic configured to enable the tristate buffers to drive a byte-wise section of N-bit wide write data during a first time period.
• The complaint does not explicitly reserve the right to assert other claims.

U.S. Patent No. 11,016,918

• Patent Identification: U.S. Patent No. 11,016,918, “Flash-DRAM Hybrid Memory Module,” issued May 25, 2021.
• Technology Synopsis: The patent describes a hybrid memory module combining volatile DRAM and non-volatile Flash memory. It specifically claims a power supply architecture on the module that includes multiple buck converters and a converter circuit to provide several different regulated voltages to the various components on the board, such as the DRAM and control circuits (’918 Patent, Abstract).
• Asserted Claims: The allegations appear to read on an independent claim covering a memory module with a PCB, multiple buck converters providing distinct regulated voltages, and a converter circuit providing a fourth regulated voltage (Compl. ¶46).
• Accused Features: The complaint alleges that Micron's DDR5 memory modules (LRDIMMs, RDIMMs, etc.) infringe by including an on-module Power Management Integrated Circuit (PMIC) that uses multiple buck converters to generate the VDD, VDDQ, and VPP voltages required by the DDR5 standard (Compl. ¶46-47).

U.S. Patent No. 11,232,054

• Patent Identification: U.S. Patent No. 11,232,054, “Flash-DRAM Hybrid Memory Module,” issued January 25, 2022.
• Technology Synopsis: This patent, related to the ’918 Patent, describes a hybrid memory module with a voltage conversion circuit having at least three buck converters. It further adds a controller with a voltage monitor circuit that detects changes in the input voltage (e.g., over- or under-voltage conditions) and transitions the module to a different operable state, potentially writing data to a non-volatile register to preserve information (’054 Patent, Abstract).
• Asserted Claims: The allegations appear to read on an independent claim requiring a voltage conversion circuit with three buck converters and a controller that detects input voltage changes and transitions the module between operable states (Compl. ¶52-53).
• Accused Features: Micron's DDR5 products are accused of infringing by having a PMIC with at least three buck converters and a voltage monitoring circuit that can detect over/under-voltage conditions and transition the module to a different state, such as by recording values in a register (Compl. ¶52-53).

U.S. Patent No. 8,787,060

• Patent Identification: U.S. Patent No. 8,787,060, “Method and Apparatus for Optimizing Driver Load in a Memory Package,” issued July 22, 2014.
• Technology Synopsis: The patent describes an apparatus for high-bandwidth memory (HBM) packages with stacked dies. The invention involves using at least two different interconnect paths, each connecting a control die to a different subset of the stacked array dies. The control die selects one of two corresponding drivers to drive a data signal to a selected array die via the appropriate interconnect, optimizing the driver load (’060 Patent, Abstract).
• Asserted Claims: The allegations appear to read on an independent method claim involving receiving a data signal and a control signal, and selecting one of a first driver or a second driver to drive the data signal to a selected array die via a corresponding first or second die interconnect (Compl. ¶58).
• Accused Features: Micron’s HBM products are accused of infringing by having stacked DRAM dies where some interconnects (TSVs) connect to a first group of dies while others bypass that group to connect to a second group, and using different drivers to send signals to selected dies based on chip select signals (Compl. ¶58).

U.S. Patent No. 9,318,160

• Patent Identification: U.S. Patent No. 9,318,160, “Memory Package with Optimized Driver Load and Method of Operation,” issued August 19, 2016.
• Technology Synopsis: This patent is related to the ’060 Patent and describes a memory package with stacked array dies organized into at least two groups. It claims a control die with first and second data conduits connecting data terminals to the different groups of dies. The conduits include drivers of different sizes to account for the different distances signals must travel to reach array dies at various positions in the stack (’160 Patent, Abstract).
• Asserted Claims: The allegations appear to read on an independent claim for a memory package with at least two groups of stacked array dies, two corresponding interconnects, and a control die with first and second data conduits having drivers of different sizes (Compl. ¶63).
• Accused Features: Micron's HBM products are accused of infringing by using different driver sizes to account for the different signal travel distances to respective array dies within the stack (Compl. ¶63).

U.S. Patent No. 7,619,912

• Patent Identification: U.S. Patent No. 7,619,912, “Memory Module Decoder,” issued November 17, 2009.
• Technology Synopsis: The patent discloses a memory module with a decoder circuit that allows the module to have more ranks of memory devices than are supported by the computer system's native chip-select signals. The circuit receives a set of input signals, including fewer chip-selects than the total number of ranks, and generates a larger set of output signals to select the appropriate rank on the module (’912 Patent, Abstract).
• Asserted Claims: The allegations appear to read on an independent claim requiring a circuit on a memory module that receives input signals including chip-selects for fewer than the total number of ranks and generates output signals in response (Compl. ¶68).
• Accused Features: Micron's DDR4 LRDIMM and RDIMM products are accused of infringing because their Registering Clock Driver (RCD) implements a chip select mode where it can receive fewer input chip selects than the total number of ranks on the DIMM and generate the necessary output signals to select the correct rank (Compl. ¶68).

U.S. Patent No. 11,093,417

• Patent Identification: U.S. Patent No. 11,093,417, “Memory Module With Data Buffering,” issued August 17, 2021.
• Technology Synopsis: The patent describes a memory module with logic (e.g., an RCD) and circuitry (e.g., data buffers). The logic outputs registered address and control signals, and the data buffers transfer data between the memory bus and memory devices. The key feature is that data transfers through the buffer are registered for a time delay, causing the memory module's overall CAS latency to be greater than the actual operational CAS latency of the individual memory devices (’417 Patent, Abstract).
• Asserted Claims: The allegations appear to read on an independent claim for a memory module where circuitry introduces a time delay such that the module's overall CAS latency is greater than the operational CAS latency of its memory devices (Compl. ¶73).
• Accused Features: Micron’s DDR4 LRDIMMs are accused of infringing because their data buffers register data for an amount of time that causes the overall CAS latency of the module to be greater than the native CAS latency of the SDRAM chips themselves (Compl. ¶73).

U.S. Patent No. 9,858,215

• Patent Identification: U.S. Patent No. 9,858,215, “Memory Module With Data Buffering,” issued January 2, 2018.
• Technology Synopsis: The patent discloses a memory module with a buffer and logic that responds to distinct memory commands. In response to a first memory command, the logic provides first control signals to the buffer to enable a first data burst. In response to a subsequent second memory command, the logic provides second, different control signals to the buffer to enable a second data burst, allowing for communication with different ranks selected by different chip-select signals (’215 Patent, Abstract).
• Asserted Claims: The allegations appear to read on an independent claim for a memory module with a buffer and logic configured to provide different control signals to the buffer in response to different memory commands associated with different chip-select signals (Compl. ¶78, 32).
• Accused Features: Micron’s DDR4 LRDIMMs are accused of infringing because their buffer logic is configured to respond to a first memory command (associated with a first chip-select signal) by enabling a first data burst, and to a second command (associated with a second chip-select) by providing different control signals to enable a second data burst (Compl. ¶78, 32).

III. The Accused Instrumentality

Product Identification

• The complaint identifies three categories of accused products: (1) DDR4 LRDIMM products; (2) DDR5 memory modules (including LRDIMMs, RDIMMs, SODIMMs, and UDIMMs); and (3) High Bandwidth Memory (HBM) products (including HMB3E products) (Compl. ¶14, 34, 46, 58).

Functionality and Market Context

• The complaint describes the accused DDR4 and DDR5 products as dual in-line memory modules (DIMMs) that are industry-standard components for computer systems (Compl. ¶14). These modules include components such as a Registering Clock Driver (RCD), Synchronous Dynamic Random-Access Memory (SDRAM) devices arranged in ranks, data buffers, and, for DDR5, an on-module Power Management Integrated Circuit (PMIC) (Compl. ¶34, 40, 46, 68).
• The accused HBM products are described as high-performance memory components featuring a stack of DRAM dies interconnected with a control die via Through-Silicon Vias (TSVs) (Compl. ¶58).
• The complaint alleges these products are manufactured, used, sold, and imported by Micron in the United States and are key components in the computer, networking, storage, and consumer electronics markets (Compl. ¶9, 14, 15).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

10,860,506 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a memory module operable in a computer system to communicate with a memory controller...via a memory bus	Micron's accused DDR4 LRDIMM products are memory modules that communicate with a memory controller via a memory bus.	¶34	col. 3:20-25
a module control device on the module board configurable to receive input C/A signals...and to output registered C/A signals...	The accused products include a registering clock driver (RCD) on the module board which receives input Command/Address (C/A) signals and outputs registered C/A signals.	¶34	col. 4:39-45
memory devices arranged in multiple ranks on the module board...wherein the registered C/A signals cause a selected rank...to perform the memory read operation	The accused products have DDR4 SDRAMs arranged in multiple ranks, and registered C/A signals from the RCD cause a selected rank to perform a read operation, outputting read data and strobes.	¶34	col. 4:35-39
data buffers on the module board and coupled between the edge connections and the memory devices...	The accused DDR4 LRDIMMs include data buffers on the module board, coupled between the edge connections and the memory devices.	¶35	col. 3:29-32
a first data buffer...is configurable to...delay the first read strobe by a first predetermined amount to generate a first delayed read strobe	A first data buffer in the accused products is configurable to delay a first read strobe by a predetermined amount.	¶35	col. 10:9-15
sample the first section of the read data using the first delayed read strobe	The first data buffer is configurable to sample the first section of read data using the generated delayed read strobe.	¶35	col. 20:50-52
wherein the first predetermined amount is determined based at least on signals received by the first data buffer during one or more previous operations.	The complaint alleges that the predetermined amount of delay is determined based at least on signals received by the data buffer during previous operations.	¶35	col. 16:11-20

Identified Points of Contention

• Scope Questions: A central question may be whether the standard operation of a DDR4 LRDIMM's data buffer inherently performs the claimed function of determining a delay amount "based at least on signals received...during one or more previous operations." The defense may argue that any delay is fixed or configured at initialization according to industry standards, not dynamically determined based on "previous operations" in the manner contemplated by the patent.
• Technical Questions: What specific "signals received by the first data buffer during one or more previous operations" does Netlist contend are used to determine the delay amount in Micron's products? The complaint is general on this point, which may become a key area of technical dispute requiring expert testimony.

10,949,339 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
An N-bit-wide memory module mountable in a computer system...	Micron's DDR4 LRDIMMs are N-bit-wide memory modules.	¶40	col. 2:25-31
a module controller...configurable to receive...input address and control signals for a memory write operation...and to output registered address and control signals	The module controller (e.g., RCD) is configurable to receive input address and control signals for a write operation and output registered signals that cause a selected rank to perform the operation.	¶40	col. 2:48-55
a plurality of byte-wise buffers coupled to the PCB...	The accused DDR4 LRDIMMs are alleged to comprise a plurality of byte-wise buffers.	¶41	col. 2:56-57
each respective byte-wise buffer...has a first side...coupled to a respective set of data signal lines, a second side that is operatively coupled to at least one respective DDR DRAM device...and a byte-wise data path between the first side and the second side	Each buffer has a first side coupled to system-side data lines and a second side coupled to DRAM devices via module data lines, with a data path between them.	¶41	col. 4:50-67
the byte-wise data path includes first tristate buffers, and the logic...is configured to enable the first tristate buffers to drive the respective byte-wise section of the N-bit wide write data...during the first time period.	The logic in the accused buffers is alleged to enable tristate buffers to drive a byte-wise section of write data from the first side to the second side for a time period determined by a latency parameter.	¶41	col. 5:2-15

Identified Points of Contention

• Scope Questions: The dispute may center on whether the standard data buffers found on DDR4 LRDIMMs meet the definition of the claimed "byte-wise buffer" which includes specific "logic configurable to control the byte-wise data path." Micron may argue its components are standard data transceivers and lack the specific control logic claimed in the patent.
• Technical Questions: Does the logic in Micron's data buffers operate "in accordance with a latency parameter" to control the timing of the data path in the specific manner required by the claim? The complaint's mapping of this limitation to the accused products' operation will be a critical point of analysis.

V. Key Claim Terms for Construction

For the ’506 Patent

• The Term: "determined based at least on signals received by the first data buffer during one or more previous operations"
• Context and Importance: This phrase is the functional core of the claim, defining how the timing delay is set. The entire infringement case may hinge on whether the standard operation of Micron's data buffers meets this "determined based on...previous operations" requirement, or if the patent requires a more dynamic, learning-based timing adjustment not present in the accused products.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification states the time interval can be used "during a subsequent read operation to time transmission of read data," which could be interpreted broadly to include any timing value derived from a prior operation, even one set during initialization (’506 Patent, col. 4:15-19).
  • Evidence for a Narrower Interpretation: The detailed description discusses using a "write preamble" to determine a time interval that is then used for a subsequent read, suggesting a specific sequence of "previous" and "subsequent" operations beyond a one-time configuration setting (’506 Patent, col. 16:15-24). Practitioners may focus on this term because it appears to require a specific, dynamic functionality that may not be present in a standards-compliant product.

For the ’339 Patent

• The Term: "byte-wise buffer"
• Context and Importance: The patentability of the invention and infringement by the accused products depend on this term being construed as something more than a standard data buffer or transceiver. If the term is construed broadly to cover any buffer that handles data in byte-sized groups (which is common), infringement may be easier to show, but the claim may be vulnerable to invalidity challenges. A narrower construction may preserve validity but make infringement more difficult to prove.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claims describe the buffer as having a "byte-wise data path" and being coupled to "a respective set of data signal lines," language which could simply describe the physical reality of any buffer on a standard 8-bit wide data bus segment (’339 Patent, col. 20:43-50).
  • Evidence for a Narrower Interpretation: The abstract describes the buffers as being "controlled by the set of module control signals to actively drive respective byte-wise sections of each data signal," suggesting a level of active, granular control beyond simple data re-transmission (’339 Patent, Abstract). Practitioners may focus on this term as it is a potential neologism whose scope will be defined through the litigation.

VI. Other Allegations

Indirect Infringement

• The complaint alleges both induced and contributory infringement for all nine patents. The inducement allegations are based on Micron providing "specifications, datasheets, instruction manuals, and/or other materials that encourage and facilitate infringing use" of the accused products by customers and end users (Compl. ¶36, 42, 48, 54, 59, 64, 69, 74, 79). Contributory infringement is alleged on the basis that the accused products are a material part of the patented invention and have no substantial noninfringing use (Compl. ¶37, 43, 49, 55, 60, 65, 70, 75, 80).

Willful Infringement

• Willfulness is alleged for all nine patents based on both pre- and post-suit knowledge. The complaint alleges pre-suit knowledge based on presentations Netlist made to Micron disclosing the patented technologies as early as 2015 (Compl. ¶38, 44, 50, 56, 61, 66). It alleges post-suit knowledge based on the filing of infringement lawsuits beginning on April 28, 2021 (Compl. ¶38, 44, 50, 56, 61, 66, 71, 76, 81).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can terms such as "byte-wise buffer" (’339 Patent) and a delay "determined based on...previous operations" (’506 Patent) be construed to cover the functionality of industry-standard components like RCDs and data buffers operating according to JEDEC specifications, or do they require a specific, non-standard implementation?
• A key evidentiary question will be one of functional operation: what technical evidence can Netlist provide to demonstrate that Micron's products, which are designed for interoperability, actually perform the specific timing adjustments, logical controls, and voltage monitoring responses as affirmatively required by the patent claims, beyond merely being capable of operating in a way that might be described by the claim language?
• A central procedural question will be the impact of the case posture: how will the fact that this is a Declaratory Judgment action responding to Micron's "bad faith" suits in Idaho—rather than a direct infringement suit—influence discovery, motion practice, and the ultimate framing of the issues for the court and jury?