DCT

2:24-cv-00097

Lionra Tech Ltd v. Cisco Systems Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:24-cv-00097, E.D. Tex., 02/13/2024
  • Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant is registered to do business in Texas, has transacted business in the district, has committed alleged acts of infringement in the district, and maintains a regular and established place of business within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s networking switches and related products infringe a patent related to methods for high-speed processing of network data packets.
  • Technical Context: The technology concerns specialized methods for handling protocol headers in packet-based communications to reduce processing latency and increase data throughput in high-speed networks.
  • Key Procedural History: The complaint alleges that Plaintiff and its predecessors have not made, offered for sale, or sold products practicing the asserted patent, a fact which may be relevant to questions of patent marking and damages calculations.

Case Timeline

Date Event
2007-09-14 ’471 Patent Priority Date
2010-06-15 U.S. Patent No. 7,738,471 Issued
2024-02-13 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,738,471 - High speed packet processing in a wireless network

  • Patent Identification: U.S. Patent No. 7,738,471, "High speed packet processing in a wireless network," issued June 15, 2010.

The Invention Explained

  • Problem Addressed: In conventional packet-based networks, processing a data packet is a slow, sequential process. Each protocol layer (e.g., media access, network, transport) must wait for the layer below it to process its respective header before it can begin its own work. This sequential approach creates significant delays ("varying latencies") that are particularly detrimental in high-speed wireless networks and for battery-powered devices. (’471 Patent, col. 2:3-14, 2:56-65).
  • The Patented Solution: The invention proposes a "cross layer architecture framework" to bypass this sequential bottleneck. (’471 Patent, col. 6:1-3). After an incoming packet is decoded, a Direct Memory Access (DMA) device is used to perform a "concurrent writing step." This step involves writing each of the packet's different protocol headers simultaneously to two locations: (1) a general packet buffer memory for storage, and (2) the individual, dedicated memory of each corresponding protocol stack layer. (’471 Patent, Abstract; col. 4:5-14). This allows each protocol layer to access and process its specific header in parallel, without waiting for other layers to complete their tasks, thereby reducing overall processing time. (’471 Patent, col. 6:25-34).
  • Technical Importance: This method of enabling parallel header processing was designed to decrease processing time and increase bandwidth for the high-speed data traffic becoming common in modern wireless networks. (’471 Patent, col. 2:56-61).

Key Claims at a Glance

  • The complaint asserts independent claim 13. (Compl. ¶10).
  • The essential elements of independent claim 13, an apparatus claim for an "egress end user node," are:
    • A decoder configured for decoding a packet having a plurality of headers; and
    • A direct memory access (DMA) device coupled to the decoder and configured for concurrently writing:
      • (1) each of the plurality of headers to a packet buffer memory; and
      • (2) each individual one of the plurality of headers to a respective protocol stack layer memory where it is available for immediate processing. (’471 Patent, col. 12:35-50).
  • The complaint states that Plaintiff's infringement contentions will identify further claims. (Compl. ¶9).

III. The Accused Instrumentality

Product Identification

The complaint accuses a wide range of Cisco networking products, including but not limited to the Cisco Catalyst 9000 series switches (e.g., 9600, 9500, 9400), Nexus series switches (e.g., 9000, 7000, 3000), and various Industrial Ethernet switches. (Compl. ¶9). These are referred to collectively as the "Accused Products."

Functionality and Market Context

The complaint focuses on the "packet processing capabilities" of the Accused Products. (Compl. ¶12). It alleges these products are used in high-speed networking environments to direct data traffic. The complaint specifically references a Cisco white paper on the Catalyst 9600 Series Switches' architecture as an example of the advertised infringing functionality. This document is provided as Exhibit 3 to the complaint and describes the product’s technical capabilities. (Compl. ¶12).

IV. Analysis of Infringement Allegations

The complaint alleges that the Accused Products directly infringe at least claim 13 of the ’471 Patent. (Compl. ¶10). The complaint references an attached claim chart in Exhibit 2 that purportedly compares claim 13 to the Accused Products; however, this exhibit was not provided for this analysis. (Compl. ¶10).

The complaint's narrative theory alleges that the Accused Products, in performing their packet processing functions, necessarily contain a "decoder" and a component that functions as a "direct memory access (DMA) device." (Compl. ¶10). It is alleged that upon receiving a data packet, this hardware architecture performs the claimed "concurrently writing" step by distributing the packet’s various protocol headers to both a general buffer and to the respective processing engines or memories corresponding to different protocol layers, thereby satisfying the limitations of claim 13. (Compl. ¶10, 12). The complaint offers as evidence a link to a Cisco installation guide for the Catalyst 9600 series switches, which it alleges contains instructions for configuring the products to operate in an infringing manner. (Compl. ¶12; Ex. 4).

  • Identified Points of Contention:
    • Scope Questions: A potential dispute may arise over the proper construction of "direct memory access (DMA) device." The patent describes a "dedicated integrated circuit," which raises the question of whether the highly integrated, application-specific silicon (ASIC) architecture in a modern Cisco switch meets this limitation, either literally or under the doctrine of equivalents. (’471 Patent, col. 5:29-31).
    • Technical Questions: The core of the infringement dispute may turn on the actual operational method of the accused switches. It raises the evidentiary question of whether the accused architecture performs the specific "concurrently writing" of headers to distinct "respective protocol stack layer memor[ies]" as claimed, or if it utilizes a fundamentally different high-speed pipeline architecture (e.g., a single shared memory with parallel pointers) that falls outside the claim's scope.

V. Key Claim Terms for Construction

  • The Term: "direct memory access (DMA) device"

    • Context and Importance: This term defines a critical structural component of the claimed invention. The infringement analysis will depend heavily on whether the packet processing hardware within Cisco's ASICs, which may not be labeled as a "DMA device," nevertheless falls within the scope of this term.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the general purpose of a DMA device as allowing "peripheral devices to read or write data without involving a CPU." (’471 Patent, col. 5:32-35). A party could argue that any hardware block that achieves this data transfer function, regardless of its specific implementation, meets the definition.
      • Evidence for a Narrower Interpretation: The patent also describes a DMA device as a "dedicated integrated circuit" with "programming registers" and "DMA channels," language that suggests a conventional, discrete DMA controller architecture. (’471 Patent, col. 5:29-45). A party could argue this language limits the term to that specific structure, excluding more integrated, multi-function processing engines.

  • The Term: "concurrently writing"

    • Context and Importance: This term describes the central functional step of the invention that enables parallel processing. The dispute will likely focus on the required degree of simultaneity and the specific mechanism of the writing operation.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent states that the DMA write operations "enable concurrent header and/or data processing by each of the protocol stack layers." (’471 Patent, col. 9:12-15). This focus on the result (enabling concurrent processing) might support an interpretation that the writes need only overlap in time or be part of a single, efficient operation, rather than being perfectly simultaneous.
      • Evidence for a Narrower Interpretation: The patent describes the DMA device as allowing the transfer of data in a "single DMA transaction" and repeatedly uses the phrase "concurrently communicate data." (’471 Patent, col. 6:15-21). This could support a narrower definition requiring a specific type of parallel hardware write operation to both the packet buffer and the multiple layer memories as part of one indivisible command.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement under 35 U.S.C. § 271(b), asserting that Cisco provides "user manuals and online instruction materials" that instruct and encourage end users to configure and use the Accused Products in a manner that directly infringes the ’471 Patent. (Compl. ¶12). It also alleges contributory infringement under § 271(c), stating the Accused Products are a material part of the invention, are especially adapted for infringement, and are not staple articles of commerce suitable for non-infringing use. (Compl. ¶13).
  • Willful Infringement: Willfulness is not pleaded as a separate count, but the complaint alleges that Cisco has knowledge of the ’471 Patent and its infringement "at least as of the filing and service of this complaint" and continues to infringe despite this knowledge. (Compl. ¶12, 13). These allegations may form the basis for a claim of post-filing willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of structural equivalence: can the patent’s "direct memory access (DMA) device," described in the context of a discrete component, be construed to read on the integrated packet processing engines within the Defendant’s complex networking ASICs?
  • A key evidentiary question will be one of operational function: what technical evidence will demonstrate that the accused switches perform the specific "concurrently writing" of individual headers to distinct "protocol stack layer memor[ies]" for parallel processing, as required by Claim 13, as opposed to employing an alternative high-speed processing pipeline that is technically distinct from the claimed method?