DCT

2:24-cv-00101

KMizra LLC v. Silicon Motion Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:24-cv-00101, E.D. Tex., 02/15/2024
  • Venue Allegations: Plaintiff alleges venue is proper under the alien-venue rule (28 U.S.C. § 1391(c)(3)) because Defendant is not a resident of the United States. The complaint also asserts Defendant conducts substantial business in the district through its distribution channels and U.S.-based subsidiaries.
  • Core Dispute: Plaintiff alleges that Defendant’s NAND Flash memory controllers, used in solid-state drives and other electronic devices, infringe six patents related to high-speed signaling systems, adaptive channel calibration, and memory controller operations.
  • Technical Context: The technology concerns memory controller integrated circuits, which are essential for managing high-speed data transfer between processors and non-volatile memory like NAND flash in modern computing and consumer electronics.
  • Key Procedural History: The complaint alleges that Plaintiff's predecessor-in-interest, Rambus, provided Defendant with notice of infringement for four of the asserted patents, including claim charts, as early as September 2018. It further alleges additional notice for all six asserted patents was provided in January 2023, establishing a basis for the willfulness allegations.

Case Timeline

Date Event
2004-11-29 U.S. Patent No. 10,331,379 Priority Date
2010-01-25 U.S. Patent No. 8,183,887 Priority Date
2012-05-22 U.S. Patent No. 8,183,887 Issued
2013-03-18 U.S. Patent No. 8,693,556 Priority Date
2014-03-31 U.S. Patent No. 9,111,608 Priority Date
2014-04-08 U.S. Patent No. 8,693,556 Issued
2014-11-06 U.S. Patent No. 9,160,466 Priority Date
2015-08-18 U.S. Patent No. 9,111,608 Issued
2015-10-13 U.S. Patent No. 9,160,466 Issued
2015-11-24 U.S. Patent No. 9,437,279 Priority Date
2016-09-06 U.S. Patent No. 9,437,279 Issued
2017-04-12 U.S. Patent No. 10,331,379 Filing Date
2018-09-13 Defendant allegedly received notice of infringement for '887, '556, '466, '279 patents from Rambus
2019-06-25 U.S. Patent No. 10,331,379 Issued
2023-01-01 Defendant allegedly received notice of infringement for all six asserted patents from Rambus
2024-02-15 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,183,887 - "High speed signaling system with adaptive transmit pre-emphasis"

  • Issued: May 22, 2012

The Invention Explained

  • Problem Addressed: In high-speed signaling systems, channel imperfections and power constraints cause signal degradation (inter-symbol interference), making it difficult for a transmitter to optimally adjust its output drivers to ensure data is received correctly. ('887 Patent, col. 1:47-60).
  • The Patented Solution: The invention describes a closed-loop system where the receiver provides feedback to the transmitter. The receiver compares the incoming signal to an adaptively determined "target signal level" and sends feedback based on this comparison. The transmitter's "update circuit" then uses this feedback to adjust the "tap weights" (i.e., drive strengths) of its multiple output drivers to compensate for channel distortion. ('887 Patent, Abstract; col. 2:22-30).
  • Technical Importance: Adaptive equalization allows high-speed interfaces to maintain signal integrity over various channel conditions, a key enabling technology for standards like PCI Express that demand high data rates. (Compl. ¶44).

Key Claims at a Glance

  • The complaint asserts at least independent claim 19 (Compl. ¶42).
  • The essential elements of claim 19 are:
    • A set of drivers to transmit a digital sequence, each controlled by one of a plurality of taps.
    • An update circuit to update a tap weight for at least one tap.
    • The update is responsive to feedback from the receiver.
    • The feedback represents a setting for the tap.
    • The feedback is adjusted to compensate for a target signal level.
  • The complaint expressly reserves the right to assert additional claims (Compl. ¶42, fn. 1).

U.S. Patent No. 8,693,556 - "Communication channel calibration for drift conditions"

  • Issued: April 8, 2014

The Invention Explained

  • Problem Addressed: The optimal operating parameters of a high-speed communication channel can "drift" over time due to changes in temperature and voltage, degrading performance. Performing a full, initial calibration to correct this drift is disruptive to normal data transmission. ('556 Patent, col. 1:15-30).
  • The Patented Solution: The patent discloses a method where calibration cycles are performed "from time to time during normal operation" to track and compensate for drift. This involves determining "adjustment information" for a channel parameter (e.g., timing) while "interspersed with" normal data transmission, and then using that information to adjust the parameter's operational value. ('556 Patent, Abstract; col. 3:6-20).
  • Technical Importance: This technology enables communication systems to maintain optimal performance and reliability as operating conditions change, without requiring significant downtime for recalibration. (Compl. ¶63).

Key Claims at a Glance

  • The complaint asserts at least independent claim 10 (Compl. ¶58).
  • The essential elements of claim 10 are:
    • An interface for a communication channel.
    • Logic to apply a parameter associated with data transmission.
    • Logic to process a calibration sequence to establish an operation value for the parameter.
    • Logic to determine adjustment information for the parameter, interspersed with data transmission or reception.
    • Logic to adjust the operation value using the adjustment information.
  • The complaint expressly reserves the right to assert additional claims.

U.S. Patent No. 9,111,608 - "Strobe-offset control circuit"

  • Issued: August 18, 2015
  • Technology Synopsis: The invention addresses timing skew between a data strobe signal (DQS) and individual data lines (DQ) in a memory interface, which can arise from unmatched signal path lengths. The patented solution is a memory controller with individually adjustable delay elements for each data signal, allowing each signal to be precisely aligned with the strobe signal before it is sampled by the receiver. (Compl. ¶¶ 79-82; ’608 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 (Compl. ¶77).
  • Accused Features: The accused functionality is the DQS-DQ training procedure in controllers supporting the LPDDR4 standard, which is alleged to individually train delays for each DQ signal to compensate for timing mismatches with the DQS strobe signal (Compl. ¶¶ 75, 80).

U.S. Patent No. 9,160,466 - "Periodic calibration for communication channels by drift tracking"

  • Issued: October 13, 2015
  • Technology Synopsis: The patent describes a two-tiered calibration method to counteract parameter drift from environmental changes. It involves an initial, comprehensive calibration to establish a baseline operating value, followed by periodic, shorter calibration sequences to track drift from that baseline and update the value, with the shorter calibration being less time-consuming than the initial one. (Compl. ¶¶ 99-101; ’466 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 (Compl. ¶97).
  • Accused Features: The accused functionality is the ZQ calibration mechanism in flash and DRAM controllers. The complaint alleges that the ZQ Calibration Long (ZQCL) command performs the initial calibration, and the shorter ZQ Calibration Short (ZQCS) command performs the periodic drift-tracking calibration. (Compl. ¶¶ 95, 99-100).

U.S. Patent No. 9,437,279 - "Memory controller with clock-to-strobe skew compensation"

  • Issued: September 6, 2016
  • Technology Synopsis: The invention addresses timing skew between a system clock and a data strobe signal as they propagate to a memory device. The solution involves a timing calibration operation (e.g., write leveling) where the memory controller sends a sequence of differently delayed strobe signals to the memory IC, which provides feedback, allowing the controller to identify and select the optimal delay to compensate for the skew. (Compl. ¶¶ 117-118; ’279 Patent, Abstract).
  • Asserted Claims: At least independent claim 11 (Compl. ¶114).
  • Accused Features: The accused functionality is the implementation of the "write leveling" procedure in memory controllers supporting DDR3, DDR4, DDR5, and LPDDR3 standards, which is alleged to align the data strobe (DQS) with the clock at the DRAM pin. (Compl. ¶¶ 112, 117-118).

U.S. Patent No. 10,331,379 - "Memory controller for micro-threaded memory operations"

  • Issued: June 25, 2019
  • Technology Synopsis: The patent addresses inefficiencies in memory access by enabling finer-grained data transfers, or "micro-threading." It claims a memory controller that schedules memory commands using different, specifically defined time intervals for back-to-back accesses depending on whether those accesses are to banks within the same "bank group" or to different bank groups, allowing for more efficient data handling. (Compl. ¶¶ 137-138; ’379 Patent, Abstract).
  • Asserted Claims: At least independent claim 1 (Compl. ¶132).
  • Accused Features: The accused functionality is found in DDR4 memory controllers, which are alleged to implement the DDR4 standard's requirement for different timing intervals (tRRD_L vs. tRRD_S and tCCD_L vs. tCCD_S) for accesses to the same versus different bank groups. (Compl. ¶¶ 130, 137-138).

III. The Accused Instrumentality

Product Identification

  • The accused products for the ’887 Patent are SMI's SSD Controllers having a PCIe 3.0 or later interface, with the SM2262EN identified as an exemplary product (Compl. ¶40). The accused products for the ’556 Patent are SMI's controllers with LPDDR3 and/or LPDDR4 functionality, with the SM2270 identified as exemplary (Compl. ¶56).

Functionality and Market Context

  • The accused products are NAND flash memory controllers, which act as the interface between a host system (like a PC or smartphone) and the flash memory storage (Compl. ¶3). The complaint alleges the SM2262EN controller implements the PCI Express (PCIe) 3.0 standard, which requires a transmitter equalization mode to ensure signal integrity at high data rates (Compl. ¶44). A product brief for the accused SM2262EN controller identifies it as a "PCIe Gen3" device (Compl. p. 13). The complaint alleges the SM2270 controller implements the LPDDR3 standard, which includes a "write leveling" procedure to manage timing relationships between clock and data strobe signals (Compl. ¶61). Defendant is alleged to be a "global leader" in this market (Compl. ¶3).

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,183,887 Infringement Allegations

Claim Element (from Independent Claim 19) Alleged Infringing Functionality Complaint Citation Patent Citation
a set of drivers to transmit a digital sequence to a receiver, each driver controlled in association with one of a plurality of taps The accused controllers support the PCIe 3.0 standard, which requires a coefficient-based equalization mode using a multi-tap Finite Impulse Response (FIR) filter to transmit signals. ¶44 col. 5:2-20
an update circuit to update a tap weight associated with at least one of the plurality of taps responsive to feedback from the receiver The PCIe 3.0 specification allegedly provides that tap coefficients are "controllable via messaging from the receiver via an equalization procedure." ¶45 col. 8:43-50
the feedback representing a setting for the at least one of the plurality of taps The complaint alleges that the "Transmitted Preset" bits communicated during the PCIe equalization procedure represent the claimed feedback setting. ¶46 col. 9:15-18
the feedback adjusted to compensate for a target signal level The complaint alleges that the equalization formula specified in the PCIe standard adjusts the output signal based on the feedback to achieve a target signal level at the receiver. ¶46 col. 12:3-10
  • Identified Points of Contention:
    • Scope Questions: A primary question may be whether the link training and coefficient negotiation protocol defined in the PCIe 3.0 standard constitutes "feedback adjusted to compensate for a target signal level" as the term is used in the patent. The patent's specification describes a system where the target level itself is adaptively determined based on received signal characteristics, which may raise a question of whether the standardized PCIe procedure performs the same function.
    • Technical Questions: The infringement theory relies heavily on the language of the PCIe 3.0 standard. A technical question for the court will be what evidence demonstrates that the accused products' "update circuit" actually performs the function of adjusting feedback to compensate for a "target signal level" in the manner claimed, beyond merely complying with the standard's equalization protocol. The complaint provides a diagram from the PCIe 3.0 specification illustrating the three-tap FIR filter relationship used for transmitter equalization (Compl. p. 14, Fig. 4-41).

U.S. Patent No. 8,693,556 Infringement Allegations

Claim Element (from Independent Claim 10) Alleged Infringing Functionality Complaint Citation Patent Citation
an interface for a communication channel The accused SM2270 controller includes a DRAM controller interface for communication with DRAM. ¶60 col. 4:50-55
logic to apply a parameter associated with transmission of data on the communication channel The controller applies the "write leveling" procedure from the LPDDR3 standard, which adjusts the "clock to data strobe signal timing relationship," the alleged parameter. ¶61 col. 2:25-30
logic to process a calibration sequence to establish an operation value that represents the parameter, and to transmit or receive data in accordance with the operation value The controller is alleged to process the write leveling calibration sequence to establish the clock-to-strobe offset value and then uses that value for data transmission. ¶62 col. 3:6-10
logic to determine adjustment information for the parameter, interspersed with said transmission or reception of data on the communication channel The complaint alleges, upon information and belief, that write leveling is performed periodically during operation to account for temperature and voltage drift, and is therefore interspersed with normal data transmission. ¶63 col. 1:24-28
logic to adjust the operation value for the parameter using said adjustment information The complaint alleges, upon information and belief, that the controller includes logic to adjust the operational value based on the adjustment information determined during the periodic write leveling. ¶64 col. 4:1-4
  • Identified Points of Contention:
    • Factual Questions: The complaint's allegation that write leveling is performed "interspersed" with data transmission to account for drift is made on "information and belief." A central factual dispute may be whether the accused products perform this calibration only at initialization or if they do, in fact, perform it periodically during normal operation as the claim requires.
    • Scope Questions: It may be contested whether the standard "write leveling" procedure, a specific timing alignment process, meets the claim limitation of "determin[ing] adjustment information for the parameter" to account for "drift."

V. Key Claim Terms for Construction

  • For the ’887 Patent:

    • The Term: "feedback adjusted to compensate for a target signal level"
    • Context and Importance: This term is central to infringement. Its construction will determine whether the negotiated coefficient exchange in the PCIe equalization standard is equivalent to the adaptive feedback mechanism described in the patent. Practitioners may focus on this term because the patent specification heavily emphasizes an adaptively determined "data level threshold" (DLEV), which may not be present in the accused PCIe protocol.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent abstract states a goal of configuring drivers "according to whether the first signal exceeds the threshold level," which could be argued to encompass any feedback that helps optimize the signal level at the receiver. ('887 Patent, Abstract).
      • Evidence for a Narrower Interpretation: The detailed description repeatedly links the "target signal level" to the specific concept of an adaptive "data level threshold (DLEV)" that converges to the attenuated signal level of high-frequency data patterns, suggesting a more limited scope. ('887 Patent, col. 9:5-10).

  • For the ’556 Patent:

    • The Term: "interspersed with said transmission or reception of data"
    • Context and Importance: The definition of "interspersed" is critical because the infringement allegation hinges on the accused write leveling procedure occurring periodically during operation, not just at startup. Practitioners may focus on this term because the complaint pleads this element on "information and belief," signaling it as a likely point of factual and legal dispute.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent's background explains the problem as compensating for "drift of conditions... during operation," suggesting that any calibration occurring after initialization could be considered "interspersed." ('556 Patent, col. 1:21-23).
      • Evidence for a Narrower Interpretation: The patent abstract describes executing calibration cycles "from time to time during normal operation," which could be construed to require that calibration events occur between active data transmission events, not merely during idle periods.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that Defendant induces infringement by providing customers with products along with advertisements, user manuals, and technical documentation that allegedly instruct and encourage the use of the accused functionality (e.g., enabling PCIe equalization or LPDDR features) in an infringing manner (Compl. ¶¶ 48, 67).
  • Willful Infringement: The complaint alleges willful infringement based on Defendant's alleged pre-suit knowledge of the asserted patents. It cites specific communications from Plaintiff's predecessor-in-interest to Defendant, beginning around September 2018, that allegedly included claim charts demonstrating infringement by Defendant's products (Compl. ¶¶ 34, 50).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue across multiple patents will be one of definitional scope: can standardized communication protocols implemented by the accused controllers (e.g., PCIe equalization, LPDDR write leveling, DDR4 bank group timing) be construed to meet the specific functional requirements of the patent claims, or do these standards-based procedures represent distinct, non-infringing technologies?
  • A key evidentiary question, particularly for the patents concerning drift compensation, will be the actual, operational behavior of the accused controllers: will discovery prove that the devices perform periodic, drift-compensating calibrations interspersed with normal data transmission, as alleged on "information and belief" and required by certain claims, or is such calibration limited to device initialization?