InnoMemory LLC v. Zions Bancorp NA

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Zions Bancorporation, N.A. (Texas)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00144, E.D. Tex., 02/29/2024
• Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains an established place of business in the Eastern District of Texas and has committed alleged acts of infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant infringes two patents related to the architecture and power management of semiconductor memory devices.
• Technical Context: The patents address methods for improving power efficiency in Dynamic Random Access Memory (DRAM) through flexible data retrieval modes and selective memory refresh operations, which are critical technologies in modern computing.
• Key Procedural History: The complaint does not mention any prior litigation, inter partes review proceedings, or licensing history related to the patents-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle"

• Patent Identification: U.S. Patent No. 6,240,046, "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle," issued May 29, 2001.

The Invention Explained

• Problem Addressed: The patent describes a technical problem in prior art memory devices that were inefficient in terms of power consumption. Devices that retrieved multiple data words on every read cycle wasted power when only one word was needed (a random read), as the extra data was often discarded. Conversely, devices retrieving only one word at a time were less efficient for sequential (burst) reads. (’046 Patent, col. 2:3-15).
• The Patented Solution: The invention is a random access memory architecture that can operate flexibly to save power. It includes a control mechanism, such as a flip-flop, that allows the memory circuit to retrieve only a single data word for random reads but retrieve more than one data word for burst reads. This adaptability is intended to provide "statistically lower average power consumption" by matching the retrieval mode to the type of memory access request. (’046 Patent, Abstract; col. 2:45-56).
• Technical Importance: This approach offers a power-saving advantage by tailoring the memory's operational intensity to the specific nature of the data request, a significant consideration for portable and power-sensitive computing systems. (’046 Patent, col. 2:16-19).

Key Claims at a Glance

• The complaint alleges infringement of "one or more claims" without specifying which ones (Compl. ¶12). Independent claim 1 is representative:
• An integrated circuit comprising:
  • a memory array capable of storing a plurality of data words;
  • a data bus coupled to the memory array, having a width of more than one data word; and
  • wherein the circuit is capable of retrieving a first data word in a first clock cycle and a second data word in a second, immediately following clock cycle.

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

• Patent Identification: U.S. Patent No. 7,057,960, "Method and architecture for reducing the power consumption for memory devices in refresh operations," issued June 6, 2006.

The Invention Explained

• Problem Addressed: The patent addresses the power consumed by conventional memory devices during standby or low-power modes. Such devices typically refresh all memory cells to prevent data loss, even when only a portion of the stored data needs to be retained. This full-array refresh activates all associated periphery circuits, consuming unnecessary power. (’960 Patent, col. 1:15-44).
• The Patented Solution: The invention describes a method and architecture where the memory array is divided into multiple sections. Control circuitry is provided to perform background operations, such as refresh, on a selective subset of these sections while leaving the periphery circuits for the other sections inactive. This selective activation is controlled by one or more control signals, which can be programmed to define which portion of the memory is refreshed. (’960 Patent, Abstract; col. 2:36-51).
• Technical Importance: This selective refresh method reduces standby power consumption, which is a critical factor for extending battery life in mobile and portable electronic devices. (’960 Patent, col. 1:30-38).

Key Claims at a Glance

• The complaint asserts "one or more claims" without specification (Compl. ¶18). Independent claim 1 is representative:
• A method for reducing power consumption during background operations in a memory array with multiple sections, comprising the steps of:
  • controlling background operations in each section in response to one or more control signals, where the signals are generated in response to a programmable address signal;
  • wherein said background operations can be enabled simultaneously in two or more sections independently of any other section; and
  • presenting the control signals and decoded address signals to one or more periphery array circuits of the sections.

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products, services, or methods by name (Compl. ¶¶12, 18). It refers to "Exemplary Defendant Products" that are purportedly detailed in Exhibits 3 and 4; these exhibits were not filed as part of the public complaint.

Functionality and Market Context

The complaint provides no description of the functionality, operation, or market context of any accused instrumentality.
No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits (Exhibits 3 and 4) that were not provided with the publicly filed document (Compl. ¶¶14, 20). Therefore, a detailed claim chart summary cannot be constructed. The infringement theory is asserted entirely through incorporation by reference of these missing exhibits (Compl. ¶¶15, 21).

Identified Points of Contention

Based on the nature of the patents and the identity of the parties, the infringement analysis raises several threshold questions.

• Technical Questions: A primary question will be evidentiary. As the Defendant is a financial institution and not a semiconductor manufacturer, the complaint raises the question of what proof will be offered that the third-party memory components within Defendant’s unspecified products practice the specific internal architectures and operational methods required by the asserted claims.
• Scope Questions: For the ’960 patent, a key legal question may arise from its status as a method claim. The analysis may center on whether an end-user of computer equipment, such as the Defendant, can be said to "perform" the claimed internal method steps of "controlling" and "presenting" signals within a memory device, or whether such actions are performed solely by the device itself or its controller, potentially implicating questions of divided infringement or the proper identity of the direct infringer.

V. Key Claim Terms for Construction

The complaint does not provide sufficient detail for analysis of specific claim terms in the context of an accused product. However, based on the patent language, certain terms may become central to the dispute.

’046 Patent

The Term

"retrieving a first data word ... in a first clock cycle and a second data word ... in a second clock cycle immediately following the first clock cycle" (Claim 1)

Context and Importance

This language defines the specific timing and sequence of data access. Practitioners may focus on this term because the claimed capability depends on distinct actions occurring in consecutive clock cycles. The defense may scrutinize whether an accused system's data retrieval mechanism precisely maps onto this two-cycle, sequential limitation.

Intrinsic Evidence for Interpretation

• Evidence for a Broader Interpretation: The Summary of the Invention describes the capability broadly as retrieving a first word in a first cycle and a second in a second cycle, suggesting a fundamental operational sequence. (’046 Patent, col. 2:25-29).
• Evidence for a Narrower Interpretation: The specification also describes an embodiment where "two 36-bit words can be retrieved from the memory array in the first cycle." (’046 Patent, col. 2:35-37). While this describes a different mode of operation, a party could argue that the patent distinguishes between multi-word retrieval within a single cycle and the specific two-cycle sequence required by Claim 1, suggesting the claim language should be narrowly applied only to the latter.

’960 Patent

The Term

"background operations" (Claim 1)

Context and Importance

The scope of the method claim is limited to "background operations." Practitioners may focus on this term because its definition will determine what types of memory activities fall within the claim. The dispute will likely concern whether the term is limited to the patent's primary example of memory refresh or can be construed more broadly.

Intrinsic Evidence for Interpretation

• Evidence for a Broader Interpretation: The term itself is general and not explicitly limited to "refresh" in the claim language, which could support an interpretation covering other automated, non-user-initiated memory management tasks. (’960 Patent, col. 8:40-41).
• Evidence for a Narrower Interpretation: The patent's title, abstract, and background sections consistently frame the invention in the context of "refresh operations" to reduce power consumption during standby modes. This consistent focus could support an argument that "background operations" should be construed as being limited to such refresh-related activities. (’960 Patent, Title; Abstract; col. 1:15-18).

VI. Other Allegations

The complaint does not contain allegations of indirect or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

The complaint as filed presents several fundamental, open questions that will likely define the early stages of the litigation.

• A primary issue will be one of proper party: can direct infringement allegations against the Defendant, a financial institution and end-user of hardware, be sustained for claims directed to the internal architecture ('046 Patent) and operational methods ('960 Patent) of semiconductor components supplied by third parties?
• A second key issue will be evidentiary: given the absence of any specific accused product identification in the complaint, the case will depend on what discovery reveals about the memory technologies used by the Defendant and whether Plaintiff can map the claim elements onto those specific components.
• A central question of claim scope for the '960 patent will be the definition of "background operations." The dispute may focus on whether this term is limited to the patent's principal example of memory refresh in low-power modes or can be construed to cover a wider range of automated functions in the accused systems.