InnoMemory LLC v. Truist Financial Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Truist Financial Corporation (North Carolina)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00146, E.D. Tex., 08/15/2024
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant maintains an established place of business in Plano, Texas, and has allegedly committed acts of patent infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant infringes two patents related to methods and architectures for improving the performance and power efficiency of random access memory circuits.
• Technical Context: The technology at issue concerns fundamental aspects of dynamic random access memory (DRAM) design, focusing on reducing power consumption during read and refresh operations, which is critical for both battery-powered devices and large-scale computing systems.
• Key Procedural History: The complaint is a First Amended Complaint. The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date	Event
1999-02-13	’046 Patent Priority Date
2000-02-11	’046 Patent Application Filing Date
2001-05-29	’046 Patent Issue Date
2002-03-04	’960 Patent Priority Date
2003-07-29	’960 Patent Application Filing Date
2006-06-06	’960 Patent Issue Date
2024-08-15	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle"

The Invention Explained

• Problem Addressed: The patent’s background section states there was an “increasing need for memory with reduced power consumption” and for systems with “increased speed” (Compl. ¶10; ’046 Patent, col. 1:65-67). Prior art memory systems were often inefficient, either by using a narrow data bus that required a new read cycle for each data word or by using a wider bus that retrieved multiple data words at once and discarded any that were not immediately requested, wasting power (Compl. ¶11-12; ’046 Patent, col. 1:67-2:11). This created an “unfilled need for memory devices with low power consumption characteristics” (Compl. ¶13; ’046 Patent, col. 2:13-15).
• The Patented Solution: The invention is a random access memory (RAM) circuit with a data bus wider than one data word that is capable of retrieving a first data word in a first clock cycle and a second data word in a second, immediately subsequent clock cycle (Compl. ¶14; ’046 Patent, col. 2:18-28). This architecture provides flexibility to save power by retrieving only a single data word for random read requests, while also saving power on sequential "burst" requests by retrieving more than one data word in a single memory array access and saving the second word for the next cycle ('046 Patent, Abstract).
• Technical Importance: This approach enabled memory systems with both increased speed and reduced power consumption compared to conventional architectures (Compl. ¶17).

Key Claims at a Glance

• The complaint asserts infringement of at least Claim 1 ('046 Patent, col. 100:1-15; Compl. ¶18).
• The essential elements of independent Claim 1 are:
  • A random access memory integrated circuit, comprising:
  • a memory array capable of storing a plurality of data words; and
  • a data bus coupled to the memory array, the data bus having a width of more than one data word;
  • wherein the random access memory integrated circuit is capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first clock cycle...
• The complaint alleges infringement of "one or more claims," which may indicate an intent to assert dependent claims as the case develops (Compl. ¶30).

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

The Invention Explained

• Problem Addressed: The patent describes that conventional dynamic semiconductor memory devices were configured to refresh all memory cells, which made it difficult to reduce power consumption in standby mode (Compl. ¶21; ’960 Patent, col. 1:49-53). This was particularly inefficient when only a partial refresh was needed, as the "periphery array circuits of all four quadrants are activated when less than the full array requires refreshing" (Compl. ¶22, ¶26; ’960 Patent, col. 2:25-29). This created a need to reduce power consumption in battery-powered devices (Compl. ¶23; ’960 Patent, col. 2:30-32).
• The Patented Solution: The patented invention provides a method and architecture for reducing standby current in a memory device "by reducing the periphery array circuitry activated during a partial array refresh" (Compl. ¶25; ’960 Patent, col. 7:62-65). The method involves controlling background operations, such as refresh, in a plurality of sections of the memory array, allowing these operations to be enabled in two or more sections "independently of any other section" (Compl. ¶27; ’960 Patent, col. 8:50-61). This permits the activation of fewer than all sections of the memory array, thereby reducing power consumption (Compl. ¶24).
• Technical Importance: This method directly addressed the need for lower power consumption in portable, battery-powered terminals that use dynamic semiconductor memory (Compl. ¶23).

Key Claims at a Glance

• The complaint asserts infringement of at least Claim 1 ('960 Patent, col. 8:50-61; Compl. ¶27).
• The essential elements of independent Claim 1 are:
  • A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of:
  • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said...background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
  • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.
• The complaint alleges infringement of "one or more claims," suggesting dependent claims may also be at issue (Compl. ¶35).

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products, systems, or services by name. It refers to "Exemplary Defendant Products" that are purportedly identified in claim chart exhibits attached to the complaint as Exhibit 3 and Exhibit 4 (Compl. ¶30, ¶32, ¶35, ¶37). These exhibits were not provided.

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the accused instrumentality's functionality. It alleges that the "Exemplary Defendant Products practice the technology claimed by the '046 Patent" and the "'960 Patent" and that Defendant's employees "internally test and use these Exemplary Products" (Compl. ¶31-32, ¶36-37). No allegations are made regarding the products' market context or commercial importance.

IV. Analysis of Infringement Allegations

The complaint incorporates infringement claim charts by reference as Exhibits 3 and 4 but does not include them in the provided filing (Compl. ¶33, ¶38). The following summarizes the narrative infringement theory presented in the complaint.

’046 Patent Infringement Allegations

The complaint alleges that Defendant’s products infringe by embodying the "inventive and unconventional concepts" of the ’046 Patent, which are reflected in the limitations of Claim 1 (Compl. ¶18). The infringement theory appears to map the accused products to a memory system that includes a "memory array capable of storing a plurality of data words," a "data bus...having a width of more than one data word," and the capability of "retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first clock cycle" (Compl. ¶18).

’960 Patent Infringement Allegations

The complaint alleges that Defendant’s products infringe by practicing the method of the ’960 Patent, with the infringement theory centered on the inventive concepts of Claim 1 (Compl. ¶27). This theory appears to accuse a method of operation that involves "controlling said background operations in each of said plurality of sections of said memory array" and enabling such operations "simultaneously in two or more of said plurality of sections independently of any other section," which allows for power-saving partial array refreshing (Compl. ¶27).

No probative visual evidence provided in complaint.

Identified Points of Contention

• Evidentiary Questions: The lack of specific product identification or operational details in the complaint raises the primary question of what evidence Plaintiff will offer to show that Defendant's systems practice the specific architectural and methodological limitations of the asserted claims. For the ’960 Patent, a key question will be how Plaintiff intends to prove that the accused systems perform the active step of "controlling" background operations on a sub-array level.
• Scope Questions: For the ’046 Patent, a likely point of dispute is the scope of "a second clock cycle immediately following the first clock cycle." The analysis may question whether modern memory controllers, which manage complex pipelines, perform data retrievals in a manner that meets this strict temporal requirement. For the ’960 Patent, a central question may be the meaning of operating on memory sections "independently," which could determine whether the partial isolation in an accused system is sufficient to infringe.

V. Key Claim Terms for Construction

The Term: "a second clock cycle immediately following the first clock cycle" (’046 Patent, Claim 1)

• Context and Importance: This term's construction is critical to defining the temporal relationship required for infringement. A narrow construction requiring strict, uninterrupted, back-to-back clock cycles could limit the scope of the claim, whereas a broader construction allowing for logical succession within a burst operation could expand it. Practitioners may focus on this term because the operation of modern memory controllers and bus protocols may introduce latencies or other steps between data transfers that raise questions about whether they are "immediately following."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification discusses the invention in the context of "burst requests (i.e., a first read request immediately followed by advance requests)" and saving a second word to present "after the first word is output," which may suggest a functional sequence rather than a strict clock-edge-to-clock-edge requirement (’046 Patent, Abstract; col. 2:35-38).
  • Evidence for a Narrower Interpretation: The plain language of the claim itself is highly specific. The Summary of the Invention repeats the exact phrase "in a second clock cycle immediately following the first clock cycle," reinforcing a literal reading (’046 Patent, col. 2:27-28).

The Term: "independently of any other section" (’960 Patent, Claim 1)

• Context and Importance: The definition of "independently" will determine the degree of electrical and logical isolation required between memory sub-arrays during a background operation to fall within the claim scope. This is central to distinguishing the claimed invention from prior art and to assessing infringement by modern memory systems that may employ various forms of power gating or sectional control.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent’s stated goal is "reducing the periphery array circuitry activated during a partial array refresh" (’960 Patent, col. 7:64-65). This purpose-driven language could support a construction where any method that achieves this goal by deactivating some, but not all, peripheral circuits for a section qualifies as "independent," even without total electrical isolation.
  • Evidence for a Narrower Interpretation: The patent criticizes prior art where "periphery array circuits of all four quadrants are activated when less than the full array requires refreshing" (’960 Patent, col. 2:25-27). This contrast suggests the invention requires the non-active sections to have their corresponding peripheral circuits deactivated, pointing toward a stricter definition of independence that involves more than just the absence of a refresh command.

VI. Other Allegations

Indirect Infringement

The prayer for relief requests a judgment that Defendant has infringed "directly and indirectly" (Compl., Prayer for Relief ¶B, ¶D). However, the body of the complaint contains no factual allegations to support claims of induced or contributory infringement, such as knowledge of direct infringement or intent to encourage it. The infringement counts are explicitly for "Direct Infringement" (Compl. ¶30, ¶35).

Willful Infringement

The complaint does not contain an explicit allegation of willful infringement or facts to support pre- or post-suit knowledge of the patents. The prayer for relief requests a declaration that the case is "exceptional" for the purpose of recovering attorneys' fees under 35 U.S.C. § 285 (Compl., Prayer for Relief ¶G.i).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of technical proof: Given the absence of specific product identifications or operational details in the complaint, a key question is what evidence Plaintiff will produce to demonstrate that Defendant's general computing infrastructure utilizes memory systems that perform the precise, sequential data retrieval claimed in the ’046 Patent and the specific, sectional power-management method claimed in the ’960 Patent.
• The case may also turn on a question of definitional scope: Can the term "immediately following" from the ’046 Patent be construed to cover operations in complex, pipelined memory architectures, and can the term "independently" from the ’960 Patent be construed to read on systems that may feature partial, rather than complete, deactivation of circuitry for non-refreshed memory sections? The court's construction of these terms will likely be dispositive for infringement.