InnoMemory LLC v. Texas Capital Bancshares Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Texas Capital Bancshares, Inc. (Texas)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00147, E.D. Tex., 03/01/2024
• Venue Allegations: Plaintiff alleges venue is proper because Defendant has an established place of business in the Eastern District of Texas and has committed acts of patent infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant’s use of certain products infringes patents related to random access memory architecture, power consumption management, and refresh operations.
• Technical Context: The technology at issue involves methods for improving the power efficiency of dynamic random-access memory (DRAM) circuits, a foundational component in most modern computing and electronic devices.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046, “Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle,” Issued May 29, 2001

The Invention Explained

• Problem Addressed: The patent’s background section describes the trade-off between higher-density, lower-cost dynamic random-access memory (DRAM) and higher-performance static RAM (SRAM) ( Compl. ¶8; ’046 Patent, col. 1:24-42). It notes an unfilled need for memory devices with lower power consumption, particularly in environments like portable computing systems where retrieving more data than necessary from the memory array wastes power (’046 Patent, col. 2:10-15).
• The Patented Solution: The invention proposes a memory circuit architecture that can operate in different modes to improve power efficiency. For random memory reads, the circuit is capable of retrieving only a single data word from the memory array in one clock cycle, conserving power compared to systems that always retrieve multiple words (’046 Patent, col. 2:44-54). Conversely, for sequential "burst" requests, the circuit can retrieve more than one data word in a single clock cycle, which is more power-efficient than performing multiple separate array accesses (’046 Patent, Abstract). A flip-flop can be used to set the prevalent mode of operation based on whether access patterns are primarily random or burst-oriented (’046 Patent, col. 2:44-64).
• Technical Importance: This adaptive retrieval strategy was aimed at reducing the average power consumption of memory subsystems, a critical consideration for both battery-powered devices and high-performance computing systems of the era (’046 Patent, col. 2:16-19).

Key Claims at a Glance

The complaint does not identify any specific asserted claims, instead referring to "exemplary method claims" in an incorporated exhibit not attached to the complaint (Compl. ¶12). For analytical purposes, independent claim 9 is representative of the method described.

• Independent Claim 9 (Method):
  • retrieving one of a plurality of data words from the memory array in a read clock cycle when addressing separate single unrelated memory locations; and
  • retrieving more than one data words from the memory array in the read clock cycle when accessing bursts of related memory locations.
• The complaint states Plaintiff reserves the right to assert additional claims (Compl. ¶12).

U.S. Patent No. 7,057,960, “Method and architecture for reducing the power consumption for memory devices in refresh operations,” Issued June 6, 2006

The Invention Explained

• Problem Addressed: The patent background explains that conventional DRAMs typically refresh all memory cells to maintain data integrity, even in standby or power-down modes where only a portion of the stored data needs to be retained. This practice consumes unnecessary power, which reduces battery life in portable devices (’960 Patent, col. 1:35-50).
• The Patented Solution: The invention discloses a method for reducing power consumption by enabling selective refresh operations. The memory array is divided into multiple sections (e.g., quadrants), and the background refresh operations for each section can be controlled independently (’960 Patent, col. 2:40-45). This is achieved by using control signals to activate only the "periphery array circuits" for those sections designated for refresh, while the circuits for other sections remain inactive, thereby saving power (’960 Patent, Abstract; Fig. 3).
• Technical Importance: This architecture provides more granular power management for memory systems, allowing portions of a memory array to effectively enter a low-power state while critical data is maintained elsewhere, a key feature for improving energy efficiency (’960 Patent, col. 1:45-50).

Key Claims at a Glance

The complaint does not identify any specific asserted claims, instead referring to "exemplary method claims" in an incorporated exhibit not attached to the complaint (Compl. ¶18). For analytical purposes, independent claim 1 is representative of the method described.

• Independent Claim 1 (Method):
  • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
  • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.
• The complaint states Plaintiff reserves the right to assert additional claims (Compl. ¶18).

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products, methods, or services. It refers to "Exemplary Defendant Products" that are purportedly identified in Exhibits 3 and 4, which are incorporated by reference but were not filed with the complaint (Compl. ¶¶12, 14, 18, 20).

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the accused instrumentalities' functionality or market context. It makes only the conclusory allegation that the "Exemplary Defendant Products practice the technology claimed" by the patents-in-suit (Compl. ¶¶14, 20).

IV. Analysis of Infringement Allegations

The complaint does not provide the referenced claim chart exhibits or any narrative infringement theory beyond conclusory allegations that the accused products "satisfy all elements" of the asserted claims (Compl. ¶¶14, 20). Accordingly, a detailed analysis of the infringement allegations is not possible based on the provided documents.

No probative visual evidence provided in complaint.

V. Key Claim Terms for Construction

While the complaint provides no basis for claim construction analysis, certain terms from the representative independent claims are central to their respective technologies and may become focal points of dispute.

• ’046 Patent

  • The Term: "accessing bursts of related memory locations" (from claim 9)
  • Context and Importance: This term is critical for distinguishing between the two operational modes of the claimed power-saving method. The infringement analysis may turn on whether the memory access patterns in an accused system constitute "bursts" of "related" locations as distinct from accesses to "separate single unrelated" locations.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes burst requests as "a first read request immediately followed by advance requests" or involving "a number of sequential read operations," which could support a broad definition covering various types of sequential or patterned data access (’046 Patent, Abstract; col. 2:67–col. 3:3).
    • Evidence for a Narrower Interpretation: The patent also describes accessing "sequential addressed memory cells relative to a received ... 'load' address," language which could be used to argue for a narrower construction limited to strictly contiguous physical memory addresses (’046 Patent, col. 2:30-34).

• ’960 Patent

  • The Term: "programmable address signal" (from claim 1)
  • Context and Importance: This term defines the mechanism for controlling which sections of the memory array are refreshed. A dispute may arise over the meaning of "programmable"—specifically, whether it requires dynamic, run-time programmability or if it can be read to cover static configurations set at the firmware or system level.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes how the device "supports partial or full array refresh by programming the refresh address register 18 with the portion of the memory array 26 to be refreshed," which could support an interpretation covering any means of setting a register to control refresh scope (’960 Patent, col. 2:6-8).
    • Evidence for a Narrower Interpretation: A defendant could argue that the term "programmable" implies a level of re-configurability that is not met by a static or one-time configuration. The patent does not appear to explicitly define the term or provide embodiments that would resolve this ambiguity.

VI. Other Allegations

The complaint does not contain allegations of indirect infringement or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

The complaint’s lack of factual detail raises fundamental questions that will need to be addressed before any substantive technical dispute can be resolved.

• A primary issue will be one of evidentiary sufficiency: what specific products used by the financial institution Defendant are accused of infringement, and what technical evidence will Plaintiff present to support its conclusory allegations that these products practice the specific memory architecture and power management methods claimed in the patents-in-suit?
• A key technical question for the ’046 Patent will relate to operational functionality: assuming an accused product is identified, does its memory subsystem in fact implement the claimed dual-mode method of retrieving either a single data word or multiple data words from the memory array based on the type of memory request (e.g., random vs. burst)?
• For the ’960 Patent, a central issue will be one of programmable control: does the accused technology’s memory refresh system operate on a section-by-section basis under the control of a "programmable address signal" that designates which sections to refresh, or does it utilize a different power management scheme?