InnoMemory LLC v. Texas Bank Trust

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Texas Bank and Trust (Texas)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00148, E.D. Tex., 03/01/2024
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because the Defendant maintains an established place of business in the district.
• Core Dispute: Plaintiff alleges that Defendant’s use of certain technologies infringes patents related to memory circuit architecture, operational efficiency, and power consumption management.
• Technical Context: The patents-in-suit relate to the design and operation of Dynamic Random-Access Memory (DRAM) circuits, a fundamental component in virtually all modern computing systems, focusing on methods to improve performance and reduce power usage.
• Key Procedural History: The complaint does not mention any prior litigation, licensing history, or administrative proceedings related to the patents-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle"

• Patent Identification: U.S. Patent No. 6,240,046, "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle," issued May 29, 2001.

The Invention Explained

• Problem Addressed: The patent’s background section describes an unmet need for memory devices with low power consumption characteristics suitable for both random and sequential data access patterns, particularly in portable computing systems (’046 Patent, col. 2:9-15). Prior art memories were often optimized for either single-word retrieval (power-efficient for random reads) or multi-word retrieval (power-efficient for burst reads), but not both.
• The Patented Solution: The invention discloses a memory architecture capable of operating in two distinct modes: retrieving only a single data word from the memory array in one clock cycle, or retrieving more than one data word in a single clock cycle (’046 Patent, Abstract). A flip-flop can be used to select the mode, allowing the circuit to conserve power by retrieving a single word for random accesses but retrieving multiple words for sequential or "burst" accesses, thereby reducing the number of power-intensive array operations (’046 Patent, col. 2:45-58).
• Technical Importance: This flexible approach to data retrieval aimed to provide power efficiency for the mixed-access workloads common in computing devices, balancing performance needs with battery life constraints (’046 Patent, col. 2:9-15).

Key Claims at a Glance

• The complaint does not identify specific claims, instead referring to "Exemplary '046 Patent Claims" detailed in an external exhibit not provided with the complaint (Compl. ¶12, ¶14). Independent claim 1 is representative of the patent's core concept.
• Independent Claim 1:
  • A random access memory integrated circuit, comprising:
  • a memory array capable of storing a plurality of data words;
  • a data bus coupled to the memory array, the data bus having a width of more than one data word;
  • wherein the random access memory integrated circuit is capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first clock cycle...

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

• Patent Identification: U.S. Patent No. 7,057,960, "Method and architecture for reducing the power consumption for memory devices in refresh operations," issued June 6, 2006.

The Invention Explained

• Problem Addressed: The patent’s background section notes that conventional DRAMs refresh all memory cells during standby mode, even when only a portion of the memory contains data that needs to be retained (’960 Patent, col. 1:35-56). This results in unnecessary power consumption, which is a significant drawback for battery-powered mobile devices.
• The Patented Solution: The invention proposes a method and architecture for partial array refresh, where the memory array is divided into multiple sections (’960 Patent, col. 2:38-40). The system uses control signals to selectively activate the "periphery array circuits" for only those sections that require a background operation like a refresh, while leaving the circuits for other sections inactive (’960 Patent, Abstract; col. 2:40-55). This control can be based on a programmable address signal, allowing a user or system to specify which portion of memory to maintain.
• Technical Importance: This method allows for a significant reduction in standby power consumption by refreshing only the necessary parts of a memory array, extending battery life in devices where persistent memory requirements are smaller than the total memory capacity (’960 Patent, col. 1:50-56).

Key Claims at a Glance

• The complaint does not identify specific claims, instead referring to "Exemplary '960 Patent Claims" detailed in an external exhibit not provided with the complaint (Compl. ¶18, ¶20). Independent claim 1 is representative of the patent's core concept.
• Independent Claim 1:
  • A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of:
  • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals...
  • wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
  • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.

III. The Accused Instrumentality

Product Identification

• The complaint does not identify any specific accused products, methods, or services by name (Compl. ¶¶12, 18). It alleges that the "Exemplary Defendant Products" are identified in claim chart exhibits incorporated by reference.

Functionality and Market Context

• The complaint does not provide sufficient detail for analysis of the accused instrumentality's functionality or market context. The infringement allegations are contained entirely within external exhibits that were not provided (Compl. ¶¶14-15, 20-21).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint's infringement allegations are made by incorporating by reference claim charts provided as Exhibit 3 (for the ’046 Patent) and Exhibit 4 (for the ’960 Patent) (Compl. ¶15, ¶21). As these exhibits were not provided, a detailed analysis of the infringement allegations is not possible.

V. Key Claim Terms for Construction

For the ’046 Patent

• The Term: "retrieving a... data word from the memory array in a... clock cycle"
• Context and Importance: This term is central to defining the patented operation. A key dispute may arise over whether an accused device performs two distinct retrieval operations from the memory array in two sequential clock cycles, versus performing a single, wider retrieval in one cycle and merely presenting the data words sequentially at the output pins. Practitioners may focus on this term because the location and timing of the "retrieval" action—from the core array itself—is the basis for the claimed power savings.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The Summary of the Invention describes the capability in general terms, stating the memory is "capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle" ('046 Patent, col. 2:24-29).
  • Evidence for a Narrower Interpretation: The specification distinguishes this operation from prior art that "retrieves both data words" in a single read cycle and discards the second if unneeded ('046 Patent, col. 2:5-11). This suggests "retrieving... in a... clock cycle" requires a discrete access to the memory array itself, rather than just managing data already retrieved.

For the ’960 Patent

• The Term: "controlling said background operations in each of said plurality of sections... in response to one or more control signals"
• Context and Importance: This phrase defines the core inventive concept of selective refresh. The infringement analysis will likely depend on whether the accused devices possess a mechanism to actively and independently control background operations on a granular, per-section basis, and whether this control is driven by specific "control signals" as opposed to more general power-saving states.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term "background operations" is defined broadly, and the summary describes the invention as "controlling the background operations in one or more sections" ('960 Patent, col. 2:40-44).
  • Evidence for a Narrower Interpretation: The detailed description and figures illustrate a specific embodiment where four quadrants are controlled by four discrete refresh signals ("REF0-REF3") generated by a control circuit ('960 Patent, FIG. 3; col. 4:8-14). A defendant may argue that "controlling... in response to... control signals" requires a specific command-and-control architecture similar to the one disclosed, not just a passive power-down of unused memory blocks.

VI. Other Allegations

• Indirect Infringement: The complaint alleges only "Direct Infringement" and does not plead facts to support claims for either induced or contributory infringement (Compl. ¶12, ¶18).
• Willful Infringement: The complaint does not contain an allegation of willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

• A primary issue will be one of evidentiary sufficiency: The complaint makes only conclusory allegations of infringement, incorporating all factual detail by reference to external exhibits. A key threshold question is whether these non-public claim charts contain sufficient factual matter to state a plausible claim for relief under the pleading standards of Twombly and Iqbal.
• For the ’046 Patent, a key technical question will be one of operational method: Does the accused memory system perform distinct, single-word data retrievals from the core memory array in sequential clock cycles for random reads, as required by the claim, or does it utilize a different power-saving architecture, such as performing a single multi-word retrieval where unneeded data is discarded downstream from the array?
• For the ’960 Patent, a central issue will be one of architectural capability: Do the accused memory systems contain the specific architecture to selectively and independently control refresh operations on a per-section basis in response to programmable control signals, or do they achieve power savings through more general mechanisms not contemplated by the patent?