InnoMemory LLC v. Prosperity Bancshares Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Prosperity Bancshares, Inc. (Texas)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00150, E.D. Tex., 03/01/2024
• Venue Allegations: Venue is alleged to be proper as Defendant maintains an established place of business within the Eastern District of Texas and has allegedly committed acts of infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant infringes patents related to power-saving techniques in memory integrated circuits.
• Technical Context: The technology concerns methods for reducing power consumption in Dynamic Random Access Memory (DRAM) circuits, a critical component in nearly all modern electronics, by optimizing data retrieval and refresh operations.
• Key Procedural History: The complaint does not mention any prior litigation, inter partes review proceedings, or licensing history related to the patents-in-suit. The complaint also fails to identify any specific accused products, instead referring to non-proffered claim chart exhibits.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle," issued May 29, 2001

The Invention Explained

• Problem Addressed: The patent addresses the need for memory devices with low power consumption, particularly in portable computing systems. Prior art memory circuits were often inefficient, either retrieving multiple data words when only one was needed (wasting power) or requiring repeated, power-intensive memory array accesses for sequential "burst" reads ('046 Patent, col. 2:1-15).
• The Patented Solution: The invention describes a random access memory circuit that can dynamically switch between two operational modes. In one mode, it retrieves a single data word from the memory array in a clock cycle, conserving power during random access operations. In a second mode, it retrieves more than one data word in a single clock cycle, which is more power-efficient for burst read operations where sequential data is needed ('046 Patent, Abstract; col. 2:45-56). This flexibility is controlled by circuitry, such as a flip-flop, that adapts the memory's behavior to the type of read request.
• Technical Importance: This approach allows for optimizing DRAM power consumption based on the nature of the memory access (random vs. sequential), a key consideration for extending battery life in mobile and portable electronics.

Key Claims at a Glance

• The complaint asserts "one or more claims" without specifying which ones (Compl. ¶12). Independent claim 1 is representative of the core invention.
• Independent Claim 1 requires:
  • An integrated circuit comprising a memory array and a data bus wider than one data word.
  • A flip-flop with a first state and a second state.
  • In the first state, the circuit retrieves one data word from the memory array in a single clock cycle.
  • In the second state, the circuit retrieves more than one data word from the memory array in the single clock cycle.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations," issued June 6, 2006

The Invention Explained

• Problem Addressed: Dynamic memory (DRAM) cells require periodic refreshing to retain data, a process that consumes power even when a device is in standby mode. In many applications, such as portable terminals, only a portion of the total memory contains data that needs to be preserved during standby. Conventional systems that refresh the entire memory array waste power in these scenarios ('960 Patent, col. 1:41-56).
• The Patented Solution: The patent discloses a memory architecture where the memory array is divided into multiple sections (e.g., quadrants). The invention provides a method to control background operations, such as refresh, on a section-by-section basis. By activating the "periphery array circuits" for only the sections that require refreshing and leaving the circuits for other sections inactive, the system significantly reduces standby power consumption ('960 Patent, Abstract; col. 2:36-44).
• Technical Importance: This invention enables partial-array self-refresh (PASR), a foundational technology for low-power DRAM (LPDDR) that is critical for extending standby time in battery-operated devices like smartphones and laptops.

Key Claims at a Glance

• The complaint asserts "one or more claims" without specification (Compl. ¶18). Independent claim 1 is representative.
• Independent Claim 1 requires:
  • A method for reducing power consumption during background operations in a memory array having a plurality of sections.
  • Controlling the background operations in each section in response to one or more control signals.
  • The control signals are generated in response to a programmable address signal.
  • The background operations can be enabled simultaneously in two or more sections independently of any other section.
  • Presenting the control signals and decoded address signals to the periphery array circuits of the sections.
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

• Product Identification: The complaint does not identify any specific accused products, methods, or services (Compl. ¶¶12, 18). It refers to "Exemplary Defendant Products" that are purportedly identified in claim-chart exhibits, but these exhibits were not filed with the complaint (Compl. ¶¶14, 20).
• Functionality and Market Context: The complaint does not provide sufficient detail for analysis of the functionality or market context of any accused instrumentality.
• No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint makes only conclusory allegations of infringement, stating that unspecified "Exemplary Defendant Products" practice the claimed technology and satisfy all claim elements of the asserted patents (Compl. ¶¶12-14, 18-20). It incorporates by reference claim charts in Exhibits 3 and 4, which were not filed with the complaint and are therefore unavailable for analysis.

• Identified Points of Contention:
  • Scope Questions: A primary threshold question will be the identification of the accused instrumentalities. The court will need to determine what specific products are at issue and whether they contain memory circuits that perform the functions recited in the patents-in-suit.
  • Technical Questions: Without access to the claim charts or any technical description of the accused products, it is not possible to identify specific technical disputes. A central evidentiary challenge for the Plaintiff will be to demonstrate, on a limitation-by-limitation basis, how the accused, yet-unidentified, products meet the elements of the asserted claims.

V. Key Claim Terms for Construction

• Term from the ’046 Patent: "retrieves ... in a single clock cycle"

  • Context and Importance: This term appears in Claim 1 and defines the core functionality that distinguishes the two power-saving modes. The dispute may turn on what constitutes "retrieving" from the memory array versus outputting data already held in a buffer, and how a "single clock cycle" is defined and measured in the context of an accused device's operation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The Summary of the Invention describes the capability of "retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle" ('046 Patent, col. 2:23-28), which may suggest a general meaning tied to data emerging from the array per cycle.
    • Evidence for a Narrower Interpretation: The abstract distinguishes between retrieving data "from the memory array" and presenting a second data word with "no activity required of the memory array," suggesting "retrieving" requires an active memory array access, not just a buffer read ('046 Patent, Abstract).

• Term from the ’960 Patent: "periphery array circuits"

  • Context and Importance: This term appears in Claim 1 and is central to the invention, as these are the circuits that are selectively controlled to save power. Infringement will hinge on identifying corresponding structures in an accused device and determining whether they are controlled independently for different sections of a memory array.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The abstract refers generally to presenting control and address signals to "periphery array circuits of the one or more sections," which could be argued to encompass any support circuitry associated with a memory section ('960 Patent, Abstract).
    • Evidence for a Narrower Interpretation: Dependent claim 5 explicitly recites that the periphery array circuits comprise "one or more circuits from the group consisting of sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" ('960 Patent, col. 8:63-67). A defendant may argue this provides a specific, limiting definition for the term as used in the patent.

VI. Other Allegations

• Indirect Infringement: The complaint contains no factual allegations to support claims of induced or contributory infringement.
• Willful Infringement: The complaint does not allege pre- or post-suit knowledge of the patents to support a claim of willful infringement. The prayer for relief includes a request for a declaration that the case is "exceptional" under 35 U.S.C. § 285 but provides no factual basis for this request (Compl. ¶G.i).

VII. Analyst’s Conclusion: Key Questions for the Case

• A threshold issue will be one of pleading sufficiency: can the complaint survive a motion to dismiss given its failure to identify any specific accused products and its reliance on unfiled exhibits to establish a plausible claim for infringement?
• Assuming the case proceeds, a central evidentiary question will be one of functional correspondence: what specific memory components are used in Defendant’s systems, and does their operation map to the specific power-saving modes claimed in the ’046 Patent (switching between single and multi-word retrieval) and the ’960 Patent (section-specific refresh operations)?