InnoMemory LLC v. JPMorgan Chase Bank NA

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: JPMorgan Chase Bank, N.A. (New York)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00151, E.D. Tex., 03/01/2024
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant maintains an established place of business in the district and has allegedly committed acts of patent infringement there.
• Core Dispute: Plaintiff alleges that Defendant infringes two patents related to the architecture and power management of random-access memory circuits.
• Technical Context: The patents-in-suit concern fundamental technologies for improving the power efficiency of Dynamic Random-Access Memory (DRAM), a critical component in virtually all modern computing systems.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle" (’046 Patent)

The Invention Explained

• Problem Addressed: The patent describes a need for memory devices with lower power consumption, particularly in portable systems, noting that conventional memory architectures were not optimized for different types of data access. Prior art memories that retrieved multiple data words on every read cycle wasted power during random (non-sequential) access, while those retrieving only one word were less efficient for burst (sequential) access. (’046 Patent, col. 1:62-64, col. 2:1-15).
• The Patented Solution: The invention is a random access memory circuit that can operate in two modes to conserve power. For random read requests, it retrieves only a single data word from the memory array. However, for burst read requests (where sequential data is needed), it retrieves more than one data word in a single memory array access, storing the subsequent word(s) to be output in later clock cycles without requiring additional power-consuming array accesses. (’046 Patent, Abstract; col. 2:45-63). A flip-flop is described as a mechanism to switch the memory circuit between these single-word and multi-word retrieval states. (’046 Patent, col. 2:45-56).
• Technical Importance: This flexible approach allows memory systems to adapt their power consumption to the specific data access pattern, reducing energy usage in both random and burst-read scenarios, a key consideration for battery-powered electronics and other power-sensitive applications. (’046 Patent, col. 2:11-15, col. 3:6-14).

Key Claims at a Glance

• The complaint does not identify specific asserted claims but references "exemplary method claims" (Compl. ¶12). Independent claim 1 is a representative method claim.
• Independent Claim 1:
  • Providing a memory integrated circuit with a memory array and a data bus wider than one data word.
  • Retrieving a first data word from the memory array in a first clock cycle.
  • Retrieving a second data word from the memory array in a second clock cycle immediately following the first.

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations" (’960 Patent)

The Invention Explained

• Problem Addressed: In conventional DRAM, all memory cells are periodically refreshed to prevent data loss, even in standby mode. For applications where only a portion of the memory contains critical data that must be retained, refreshing the entire memory array consumes unnecessary power, which is a significant drawback for mobile and battery-powered devices. (’960 Patent, col. 1:35-56).
• The Patented Solution: The patent discloses a method and architecture for sectional power management during refresh operations. The memory array is divided into multiple sections (e.g., quadrants), and the invention allows for controlling background operations, such as refresh, on a section-by-section basis. This is achieved by selectively activating the "periphery array circuits" (e.g., sense amplifiers and drivers) only for the section(s) being refreshed, while leaving the circuitry for other sections inactive. (’960 Patent, Abstract; col. 2:40-59). Figure 3 illustrates this concept with a refresh control block capable of targeting individual quadrants (124a-124d) via separate control signals (REF0-REF3).
• Technical Importance: This selective refresh capability enables significant power savings in standby mode by allowing a device to refresh only the portions of memory that contain essential data, a critical feature for extending battery life in mobile electronics. (’960 Patent, col. 2:30-34).

Key Claims at a Glance

• The complaint does not identify specific asserted claims (Compl. ¶18). Independent claim 1 is a representative method claim.
• Independent Claim 1:
  • A method for reducing power consumption during background operations in a memory array with multiple sections.
  • Controlling background operations in each section in response to control signals generated from a programmable address signal, where operations can be enabled in two or more sections simultaneously and independently.
  • Presenting the control signals and decoded address signals to the "periphery array circuits" of the sections.

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products, services, or instrumentalities by name (Compl. ¶¶12, 18).

Functionality and Market Context

The complaint alleges infringement by "Defendant products identified in the charts incorporated into this Count below" (Compl. ¶12, ¶18). However, the referenced exhibits containing these charts (Exhibits 3 and 4) were not provided with the complaint. Consequently, the complaint itself provides no details regarding the functionality, operation, or market context of any accused instrumentality.

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint provides no narrative infringement theory or claim charts in the body of the document. It incorporates by reference external Exhibits 3 and 4, which were not provided (Compl. ¶¶15, 21). The complaint asserts only that the charts demonstrate that the "Exemplary Defendant Products practice the technology claimed" and "satisfy all elements" of the asserted claims (Compl. ¶¶14, 20). Without access to these exhibits, a detailed analysis of the infringement allegations is not possible.

Identified Points of Contention

Based on the asserted patents, potential points of contention may arise.

• ’046 Patent: An issue may be whether the accused products' handling of burst-mode data access constitutes "retrieving a second data word from the memory array in a second clock cycle" as required by the claim. The analysis may question whether accessing a pre-fetch buffer filled during a single array access meets this limitation, or if the claim requires two distinct interactions with the memory array itself.
• ’960 Patent: A central question may be one of architectural correspondence. The dispute could turn on whether the accused products' power-saving modes for memory refresh involve a memory architecture with discrete "sections" and selectively activated "periphery array circuits" as defined by the patent, or if they employ a technologically distinct power-saving method that falls outside the claim scope.

V. Key Claim Terms for Construction

’046 Patent: "retrieving a...data word from the memory array"

• Context and Importance: The construction of this term is central to defining the scope of the claimed method. The dispute will likely focus on whether this requires a distinct access to the memory array's core storage cells for each "retrieving" step or if it can broadly cover making data available on a bus from an intermediate buffer that was populated during an earlier, larger array access.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification notes that for burst requests, "power is saved by retrieving more than one data word in a clock cycle where the memory array is accessed," implying a single array access can support multiple "retrieval" events in subsequent clock cycles (’046 Patent, Abstract). The summary also states, "The second word can be saved to present to the data outputs after the first word is output," which may support reading the term broadly to include outputting from a temporary store. (’046 Patent, col. 2:38-40).
  • Evidence for a Narrower Interpretation: The claim recites "retrieving...from the memory array" for both the first and second data words. A party could argue the parallel language requires two separate, complete interactions with the physical "memory array" in two distinct clock cycles, not one access followed by a buffer read.

’960 Patent: "periphery array circuits"

• Context and Importance: This term defines the specific hardware components that are selectively controlled to save power. Its construction will determine whether the claims read on a wide range of modern memory power-saving technologies or are limited to a more specific architecture. Practitioners may focus on this term because it appears to be a term of art within the patent's context.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term is used in the abstract and claims without explicit structural limitations, suggesting it could be interpreted functionally to mean any support circuitry associated with a memory section.
  • Evidence for a Narrower Interpretation: The specification discusses conventional systems where "the periphery array circuits of all four quadrants are activated" during a refresh, suggesting the term has a specific meaning in the field (’960 Patent, col. 2:20-22). Figure 5 provides a detailed illustration of what constitutes the "periphery array circuits" (152), including wordline drivers (160), equalization circuits (162), sense amplifiers (164a-x), and column select multiplexers (166). This detailed disclosure could be used to argue for a narrower construction limited to these specific types of circuits.

VI. Other Allegations

Willful Infringement

The complaint does not explicitly allege willful infringement or plead any facts related to Defendant's knowledge of the patents-in-suit. However, the Prayer for Relief requests an award of "all appropriate damages under 35 U.S.C. § 284," the statute which provides for enhanced damages upon a finding of willfulness, and also requests that the case be declared "exceptional" under 35 U.S.C. § 285. (Compl. p. 5, ¶¶F, G.i).

VII. Analyst’s Conclusion: Key Questions for the Case

The complaint's reliance on external, unfiled exhibits for all substantive infringement allegations raises immediate procedural and evidentiary questions. Assuming the case proceeds, it will likely turn on the following core issues:

1. Evidentiary Sufficiency: The central threshold issue is whether Plaintiff can produce concrete technical evidence to support its infringement allegations. A key question for the court will be whether the functionality of any product or system used by Defendant can be mapped to the specific technical requirements of the asserted claims from the ’046 and ’960 patents.

2. Architectural Correspondence: For the ’960 Patent, a critical question will be one of architectural match. Does any accused system utilize a memory architecture with distinct, independently controllable "sections" and associated "periphery array circuits" for refresh operations, as claimed, or is there a fundamental mismatch between the patented method and the technology actually in use?

3. Operational Scope: For the ’046 Patent, the dispute may focus on definitional scope. Can the claim term "retrieving... from the memory array," which is recited for two separate clock cycles, be construed to cover the common industry practice of reading a larger block of data into a buffer in one cycle and then outputting portions of it in subsequent cycles?