InnoMemory LLC v. Capital One Financial Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Capital One Financial Corporation (Delaware)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00154, E.D. Tex., 08/21/2024
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant maintains an established place of business in the district.
• Core Dispute: Plaintiff alleges that Defendant infringes two patents related to semiconductor memory architecture designed to increase operational speed and reduce power consumption.
• Technical Context: The patents address fundamental challenges in Random Access Memory (RAM) design, where performance gains and power efficiency are critical competitive factors in components for both consumer and enterprise electronics.
• Key Procedural History: The complaint does not mention any significant prior litigation, inter partes review proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date	Event
1999-02-13	’046 Patent Priority Date
2000-02-11	’046 Patent Application Date
2001-05-29	’046 Patent Issue Date
2002-03-04	’960 Patent Priority Date
2003-07-29	’960 Patent Application Date
2006-06-06	’960 Patent Issue Date
2024-08-21	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle," issued May 29, 2001

The Invention Explained

• Problem Addressed: The patent describes a need in prior art memory systems for both "increased speed" and "reduced power consumption" (Compl. ¶10; ’046 Patent, col. 1:65-67). Conventional memories were often inefficient; those with narrow data buses required separate, power-intensive read cycles for each word, while those with wider buses retrieved multiple words at once but wasted power by discarding any data that was not immediately requested (Compl. ¶¶11-13; ’046 Patent, col. 2:1-15).
• The Patented Solution: The invention is a random access memory (RAM) circuit with a data bus wider than a single data word. This architecture allows the memory to retrieve a first data word in a first clock cycle and, if needed, a second data word in the immediately following clock cycle (Compl. ¶14; ’046 Patent, col. 2:23-28). This provides flexibility to perform efficient, high-speed "burst" reads of sequential data while also enabling power-saving single-word reads for random data access (’046 Patent, col. 3:5-20).
• Technical Importance: This approach offered a flexible memory architecture that could balance the competing demands for high-speed burst access and low-power random access, which the complaint notes was an "unfilled need" for devices like portable computing systems (Compl. ¶13; ’046 Patent, col. 2:11-15).

Key Claims at a Glance

• The complaint’s allegations focus on Claim 1 (Compl. ¶18). The complaint also contains a general allegation of infringement of one or more claims (Compl. ¶30).
• Independent Claim 1 Recites:
  • A random access memory integrated circuit having statistically lower average power consumption;
  • A memory array capable of storing a plurality of data words;
  • A data bus coupled to the memory array, having a width of more than one data word; and
  • The circuit being capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first clock cycle.

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations," issued June 6, 2006

The Invention Explained

• Problem Addressed: The patent addresses the power consumption of conventional dynamic RAM (DRAM), which required all memory cells to be periodically refreshed to maintain data integrity (Compl. ¶21; ’960 Patent, col. 1:49-53). This constant refreshing consumed significant power, particularly in standby mode, which was detrimental for battery-powered portable devices (Compl. ¶23; ’960 Patent, col. 2:30-32). A specific disadvantage noted was that conventional methods activated the "periphery array circuits of all four quadrants" even when less than the full array required refreshing (Compl. ¶22; ’960 Patent, col. 2:25-29).
• The Patented Solution: The invention provides a method for reducing power consumption by enabling partial array refreshes during background operations. The architecture allows for the selective activation of periphery circuits for a subset of the memory array's sections, such that "background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section" (Compl. ¶27; ’960 Patent, Abstract). For example, the invention may provide a capability to refresh only one-fourth or one-half of the memory array space at a time (’960 Patent, col. 7:65-8:2).
• Technical Importance: This method enabled significant power savings in DRAMs by avoiding unnecessary refresh operations on the entire memory array, which was critical for extending the continuous standby time of battery-powered portable electronics (Compl. ¶23; ’960 Patent, col. 1:53-56).

Key Claims at a Glance

• The complaint’s allegations focus on Claim 1 (Compl. ¶27). The complaint also contains a general allegation of infringement of one or more claims (Compl. ¶36).
• Independent Claim 1 Recites:
  • A method for reducing power consumption during background operations in a memory array with a plurality of sections;
  • Controlling the background operations in each section, where the operations can be enabled simultaneously in two or more sections independently of any other section; and
  • Presenting control signals to the periphery array circuits of the two or more sections.

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products, methods, or services by name. It refers to "Exemplary Defendant Products" that are purportedly detailed in Exhibits 3 and 4 (Compl. ¶¶30, 36).

Functionality and Market Context

The complaint states that these exhibits are incorporated by reference but does not attach them (Compl. ¶¶33, 39). Therefore, the complaint provides no specific details regarding the functionality or market context of the accused instrumentalities.

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not provide claim charts or detailed infringement allegations within its body. Instead, it alleges that Exhibits 3 and 4, which were not filed with the complaint, contain charts comparing the asserted claims to the "Exemplary Defendant Products" (Compl. ¶¶32, 38). The complaint’s narrative infringement theory is summarized below.

The complaint alleges that the unspecified accused products practice the technology claimed by the ’046 Patent and satisfy all elements of the asserted claims (Compl. ¶32). The infringement theory appears to rest on the allegation that the accused products incorporate a memory architecture with a data bus wider than one data word that is capable of retrieving data words in successive clock cycles, mirroring the limitations of Claim 1 (Compl. ¶18).

For the ’960 Patent, the complaint similarly alleges that the accused products practice the patented technology and meet all claim elements (Compl. ¶38). The theory centers on the allegation that these products implement a method of reducing power consumption by controlling background operations, such as refresh cycles, in different sections of a memory array independently, as recited in Claim 1 (Compl. ¶27).

• Identified Points of Contention:
  • Evidentiary Questions: The complaint’s complete reliance on non-provided exhibits raises a fundamental question of evidentiary support. A primary issue will be whether discovery reveals that the accused products, once identified, actually perform the functions recited in the asserted claims. The current allegations are entirely conclusory (Compl. ¶¶32, 38).
  • Technical Questions: Assuming products are identified that perform similar functions, a key technical question for the ’046 Patent will be whether the data retrieval mechanism operates across two distinct and "immediately following" clock cycles as required by Claim 1, or via a different timing protocol. For the ’960 Patent, a central question will be whether the accused devices possess the claimed architecture of a "plurality of sections" with periphery circuits that can be controlled independently to perform "background operations."

V. Key Claim Terms for Construction

The complaint does not provide sufficient detail about the accused products to identify likely points of contention for claim construction. However, based on the patent language, the following terms may become central to the dispute.

• ’046 Patent: "clock cycle"

  • The Term: "a first clock cycle" and "a second clock cycle immediately following the first clock cycle"
  • Context and Importance: The claim requires a specific sequential retrieval of two data words across two distinct, immediately following clock cycles. The definition of what constitutes a "clock cycle" in the context of the accused products' operation and whether the cycles are "immediately following" will be critical to the infringement analysis. Practitioners may focus on this term because this precise timing relationship is a core inventive concept distinguishing the patent from prior art that might retrieve multiple words within a single, longer cycle.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification does not appear to provide a special definition of "clock cycle," which may support an argument that the term should be given its plain and ordinary meaning to one of skill in the art of digital circuit design.
    • Evidence for a Narrower Interpretation: The specification includes detailed timing diagrams (e.g., ’046 Patent, FIG. 37) illustrating specific operational sequences in response to an "EXTERNAL CLOCK." A party may argue that "clock cycle" should be construed in light of these specific disclosed embodiments and their relationship to an external system clock.

• ’960 Patent: "background operations"

  • The Term: "background operations"
  • Context and Importance: Claim 1 is directed to reducing power consumption during "background operations." The scope of this term will determine whether the patent applies only to specific low-power states (like standby refresh) or to a wider range of activities. Practitioners may focus on this term to define the specific conditions under which the patented method is practiced.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The term itself is general. A party could argue it encompasses any operation that is not a primary, user-initiated read or write, including various system maintenance or housekeeping tasks.
    • Evidence for a Narrower Interpretation: The patent’s summary and background repeatedly link the invention to reducing "standby current" during "partial array refresh" operations (’960 Patent, col. 1:49-56, col. 7:62-65). This context suggests the term may be construed more narrowly to be limited to refresh operations performed when the device is in a standby or low-power mode.

VI. Other Allegations

The complaint does not contain allegations of indirect or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

• A primary issue will be one of evidentiary sufficiency: Can the plaintiff substantiate its conclusory infringement allegations, which currently rely entirely on non-provided exhibits, by identifying specific accused products and presenting evidence that maps their functionality to the asserted claim elements?
• A key technical question for the '046 Patent will be one of operational equivalence: Assuming an accused product retrieves multiple data words, does its memory controller execute the specific two-step retrieval across two distinct and "immediately following" clock cycles as claimed, or does it employ a fundamentally different data access protocol?
• For the '960 Patent, a central question will be one of architectural scope: Do the accused memory devices contain the claimed "plurality of sections" and independently controllable periphery circuits for performing "background operations," or do they achieve power savings through an alternative architecture that falls outside the patent’s scope?