InnoMemory LLC v. Capital One Financial Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory LLC (Texas)
  • Defendant: Capital One Financial Corp (Delaware)
  • Plaintiff’s Counsel: Rabicoff Law
• Case Identification: 2:24-cv-00154, E.D. Tex., 03/04/2024
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant maintains an established place of business in Plano, Texas, within the district.
• Core Dispute: Plaintiff alleges that Defendant infringes two patents related to power consumption and efficiency in semiconductor random access memory (RAM) devices.
• Technical Context: The patents address methods for reducing power usage in RAM, a critical component in virtually all electronic devices, by optimizing data retrieval and memory refresh operations.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date	Event
1999-02-13	’046 Patent Priority Date
2001-05-29	U.S. Patent No. 6,240,046 Issues
2002-03-04	’960 Patent Priority Date
2006-06-06	U.S. Patent No. 7,057,960 Issues
2024-03-04	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle" (issued May 29, 2001)

The Invention Explained

• Problem Addressed: The patent’s background describes a need for memory devices with lower power consumption, particularly for portable computing systems (’046 Patent, col. 2:11-15). It notes that prior art memory architectures could be inefficient; some waste power by retrieving multiple data words when only one is requested, while others are inefficient for "burst" requests that require sequential data words (’046 Patent, col. 2:1-11).
• The Patented Solution: The invention is a random access memory circuit that can operate in two distinct modes to conserve power. It can be configured to retrieve only a single data word from the memory array in one clock cycle for random read requests, minimizing power usage (’046 Patent, col. 2:60-65). Alternatively, for burst read requests where sequential data is needed, it can retrieve more than one data word in a single clock cycle, which improves efficiency (’046 Patent, col. 3:1-5). This dual-mode capability is controlled by circuitry, such as a flip-flop, that adapts the memory’s behavior to the type of data access requested (’046 Patent, col. 2:45-49).
• Technical Importance: This approach sought to provide a flexible memory architecture that could optimize power consumption for both random and sequential data access patterns, a key consideration for battery-powered electronics.

Key Claims at a Glance

The complaint refers to "exemplary method claims" identified in an exhibit not attached to the publicly filed complaint (Compl. ¶12). Independent claim 9 is a representative method claim.

• Independent Claim 9:
  • A method of reading data from a memory array, comprising:
  • retrieving one of a plurality of data words from the memory array in a read clock cycle when addressing separate single unrelated memory locations; and
  • retrieving more than one data words from the memory array in the read clock cycle when accessing bursts of related memory locations.

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations" (issued June 6, 2006)

The Invention Explained

• Problem Addressed: The patent addresses the power consumed by periodic refresh operations required to maintain data in dynamic random access memory (DRAM) cells (’960 Patent, col. 1:24-27). In standby or power-down modes, refreshing the entire memory array can be a significant power drain, which is particularly problematic for battery-powered mobile devices that may only need to retain data in a small portion of the memory (’960 Patent, col. 1:35-47).
• The Patented Solution: The invention proposes a memory architecture divided into multiple sections (e.g., quadrants) with independent control over the refresh operation for each section (’960 Patent, Abstract; Fig. 3). The memory device includes control circuitry that can activate the "periphery array circuits" for only a selected subset of these sections, allowing just those portions of the memory to be refreshed while the others remain in a low-power state (’960 Patent, col. 2:48-59). The selection of which sections to refresh is controlled by a programmable signal, allowing for flexible power management based on application needs (’960 Patent, Claim 1).
• Technical Importance: This technology enables a "partial array refresh" capability, allowing for more granular power management in DRAM by aligning refresh activity with actual data retention requirements, thereby extending battery life in portable devices.

Key Claims at a Glance

The complaint refers to "exemplary method claims" identified in an exhibit not attached to the publicly filed complaint (Compl. ¶18). Independent claim 1 is a representative method claim.

• Independent Claim 1:
  • A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of:
  • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
  • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.

III. The Accused Instrumentality

Product Identification

The complaint does not name specific accused products. It refers to "Exemplary Defendant Products" that are identified in Exhibits 3 and 4 (Compl. ¶¶ 12, 18). These exhibits were not attached to the publicly filed complaint.

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the accused products' functionality, operation, or market context.

IV. Analysis of Infringement Allegations

The complaint alleges infringement through claim charts in Exhibits 3 and 4, which were not provided (Compl. ¶¶ 15, 21). The complaint’s narrative theory of infringement states that the "Exemplary Defendant Products practice the technology claimed by the '046 Patent" and "'960 Patent," and that the products "satisfy all elements" of the asserted claims (Compl. ¶¶ 14, 20). No probative visual evidence provided in complaint.

Identified Points of Contention:

• For the ’046 Patent: The central technical question will be whether the memory controllers and/or devices used by Defendant perform the dual-mode data retrieval method of claim 9. A potential point of contention is whether the accused products distinguish between "separate single unrelated memory locations" and "bursts of related memory locations," and alter the amount of data retrieved from the memory array accordingly. The analysis may depend on whether the accused products always fetch a fixed-size block of data (e.g., a cache line) regardless of the request type, or if their retrieval behavior is adaptive as the patent claims.
• For the ’960 Patent: A primary dispute may concern whether Defendant's products implement the claimed selective, partial-array refresh. The analysis will likely focus on whether the accused devices can disable refresh operations for specific, programmable sections of a memory array by controlling their associated "periphery array circuits," as required by claim 1. Defendant’s position could be that its products employ a standard, non-programmable refresh protocol that applies to the entire memory array.

V. Key Claim Terms for Construction

• Patent: ’046 Patent (Representative Claim 9)

  • The Term: "accessing bursts of related memory locations"
  • Context and Importance: This term defines the trigger for the power-efficient, multi-word retrieval mode. Its construction is critical to determining what types of sequential memory requests fall within the scope of the claim. Practitioners may focus on this term because its definition will dictate whether common memory access patterns, such as fetching a cache line, constitute an infringing "burst."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The Abstract describes burst requests as "a first read request immediately followed by advance requests," and the summary describes them in the context of "sequential clock cycles" (’046 Patent, Abstract; col. 3:1-3). This language could support a construction where any series of consecutive read requests qualifies as a burst.
    • Evidence for a Narrower Interpretation: The specification discloses an "advance/load control" signal (ADV/LOAD#) that is used to signal a "continue the present burst" request (’046 Patent, col. 3:25-27). This could support a narrower construction requiring a specific hardware signal to initiate or continue a burst, rather than just any sequence of read operations.

• Patent: ’960 Patent (Representative Claim 1)

  • The Term: "programmable address signal"
  • Context and Importance: This term is the input that dictates which sections of the memory array are to be refreshed. The scope of "programmable" will be central to the infringement analysis. Practitioners may focus on this term to determine whether the control must be user-level software programmable or if it can be satisfied by a more limited, hardware-level configuration.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The background discusses applications where only a "portion of the total memory array has data to be retained," which suggests a need for programmability at an application or system level (’960 Patent, col. 1:41-44).
    • Evidence for a Narrower Interpretation: The specification describes a "refresh address register 18" that is programmed "with the portion of the memory array 26 to be refreshed" (’960 Patent, col. 2:1-3). This may support a narrower construction where "programmable" requires writing to a specific hardware register via a defined interface, as opposed to more general software-based control.

VI. Other Allegations

• Willful Infringement: The complaint does not explicitly allege willful infringement or plead facts indicating that Defendant had pre-suit knowledge of the patents-in-suit. While the prayer for relief requests "all appropriate damages under 35 U.S.C. § 284," it provides no factual basis to support a claim for enhanced damages (Compl. p. 5, ¶F).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A Core Evidentiary Question: The primary and immediate issue is the identification of the accused products. The complaint’s reliance on unfiled exhibits leaves the central factual basis of the lawsuit entirely unspecified. The case will depend on discovery to reveal what products are accused and to provide the technical details of their memory subsystem operation.
2. A Question of Functional Operation (’046 Patent): Does the memory access architecture in the accused products perform the claimed dual-mode retrieval method? The case may turn on whether the products' functionality matches the claim language requiring a variable amount of data to be retrieved based on a distinction between single, random accesses and "bursts" of related accesses.
3. A Question of Definitional Scope (’960 Patent): Can the partial-array refresh mechanisms in the accused products, if any, be considered controlled by a "programmable address signal"? The resolution will likely depend on construing the term "programmable" and determining whether the accused systems offer the kind of selective, configurable refresh control envisioned by the patent.