DCT

2:24-cv-00224

Eireog Innovations Ltd v. Cisco Systems Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: EireOg Innovations Limited v. Palo Alto Networks, Inc., 2:24-cv-00227, E.D. Tex., 02/26/2025
  • Venue Allegations: Venue is based on Defendant having regular and established places of business within the Eastern District of Texas, specifically in Plano, Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s Next-Generation Firewall products, which incorporate certain Intel and AMD central processing units (CPUs), infringe four patents related to processor interrupt management, cache processing, and specialized instruction handling.
  • Technical Context: The patents-in-suit relate to low-level processor architecture for managing hardware interrupts, data caching, and instruction execution, which are foundational technologies for performance and efficiency in complex computing systems like modern network security appliances.
  • Key Procedural History: The complaint indicates this is a "Member Case" filed as part of a broader litigation campaign involving a lead case against Cisco Systems, Inc. (2:24-cv-00224) and other member cases against Fortinet, Inc., and International Business Machines Corporation, suggesting a coordinated assertion of this patent portfolio against multiple defendants in the enterprise networking and security sector. No prior litigation or post-grant proceedings involving the asserted patents are mentioned in the complaint.

Case Timeline

Date Event
2009-05-07 U.S. Patent No. 8,117,399 Priority Date (Application Filing)
2010-09-21 U.S. Patent No. 8,504,777 Priority Date (Application Filing)
2012-02-14 U.S. Patent No. 8,117,399 Issued
2012-08-09 U.S. Patent No. 9,436,626 Priority Date (Application Filing)
2012-08-09 U.S. Patent No. 9,442,870 Priority Date (Application Filing)
2013-08-06 U.S. Patent No. 8,504,777 Issued
2016-09-06 U.S. Patent No. 9,436,626 Issued
2016-09-13 U.S. Patent No. 9,442,870 Issued
2025-02-26 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - "Processor interrupt interface with interrupt partitioning and virtualization enhancements"

The Invention Explained

  • Problem Addressed: The patent describes inefficiencies in data processing systems with multiple processors or virtualized environments, where processors are often delayed while vying for access to a central interrupt controller to manage hardware interrupts. This can create performance bottlenecks and add software complexity. (’971 Patent, col. 1:11-24).
  • The Patented Solution: The invention proposes moving key interrupt management functions directly onto the processor core itself. It uses on-core "special purpose registers" to store information about different software partitions (e.g., a "guest" operating system vs. a "hypervisor"). When an interrupt arrives, it includes context information like a partition identifier and priority level, which the processor core can evaluate directly against its local registers to decide whether to handle or block the interrupt without needing to access an external controller or involve the hypervisor. (’971 Patent, col. 2:15-34, Fig. 2).
  • Technical Importance: This architectural approach aims to reduce latency and software overhead in virtualized systems by enabling partitions to manage their interrupt blocking rules independently and efficiently. (’971 Patent, col. 2:23-28).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶10).
  • Essential elements of claim 1, a method claim, include:
    • Receiving, at a processor, an "interrupt package" that includes an interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier.
    • Processing the interrupt package against one or more partitions running on the processor by comparing the priority value and partition identifier against a stored priority level and partition identifier retrieved from special purpose registers at the processor.
    • Determining on a partition basis if the interrupt request is blocked or forwarded to a targeted thread.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 9,442,870 - "Interrupt priority management using partition-based priority blocking processor registers"

The Invention Explained

  • Problem Addressed: The patent addresses performance issues that arise when interrupt blocking is managed solely by a central interrupt controller. This approach can be slow and lacks the granularity needed for complex, partitioned systems where different virtual machines need to manage their own interrupt priorities. (’870 Patent, col. 1:14-26).
  • The Patented Solution: The invention describes a processor core architecture that includes dedicated, on-core priority blocking registers for different partitions (e.g., a "Guest Priority Blocking Register" and a "VMM Priority Blocking Register"). When an interrupt request arrives, its associated partition identifier is used to select the appropriate on-core register, and its priority level is compared against the value in that register to determine if the interrupt should be blocked. (’870 Patent, Abstract; col. 2:3-23; Fig. 2).
  • Technical Importance: This system allows different software partitions to control their interrupt blocking conditions independently and directly on the processor core, simplifying the design of the external interrupt controller and reducing system-wide latency. (’870 Patent, col. 2:1-4).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶20).
  • Essential elements of claim 1, a method claim, include:
    • Receiving an interrupt package for a physical interrupt request.
    • Processing the package against partitions by comparing its priority value and partition identifier against a stored priority level and partition identifier from one or more special purpose registers at the processor.
    • Determining on a partition basis if the request is blocked or forwarded.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,504,777 - "Data processor for processing decorated instructions with cache bypass"

Technology Synopsis

The patent addresses a potential data coherency problem that arises when a processor offloads certain "decorated" operations (e.g., atomic memory updates) to an intelligent memory controller. Because the memory controller modifies the data directly, the processor's cache could hold stale data. The patented solution is to have the processor bypass its cache for these specific instructions, and if a corresponding entry already exists in the cache (a cache hit), that entry is invalidated to ensure future reads fetch the correct, updated value from memory. (’777 Patent, Abstract; col. 2:48-65).

Asserted Claims

Independent claim 16. (Compl. ¶30).

Accused Features

The complaint accuses the cache processing features of products incorporating Intel CPUs (Skylake-based and newer) and AMD-based EPYC CPUs. (Compl. ¶29).

U.S. Patent No. 8,117,399 - "Processing of coherent and incoherent accesses at a uniform cache"

Technology Synopsis

The patent aims to reduce unnecessary network traffic in multi-core processors that use a unified cache for both instructions and data. The technical problem is that conventional systems keep all cached information "coherent," which requires broadcasting queries ("snoops") for every cache miss, even for instruction fetches where the data is rarely modified. The solution is to mark each cache line as either "coherent" or "incoherent." A subsequent "coherent read" (e.g., for data) that hits a line marked "incoherent" is treated as a miss, forcing a system-wide snoop to find the latest version. In contrast, an "incoherent read" (e.g., for an instruction) can hit on any matching line regardless of its coherency marking, avoiding unnecessary snoops. (’399 Patent, Abstract; col. 2:1-10).

Asserted Claims

Independent claim 14. (Compl. ¶40).

Accused Features

The complaint accuses the cache processing features of products incorporating Intel CPUs (Skylake-based and newer) and AMD-based EPYC CPUs. (Compl. ¶39).

III. The Accused Instrumentality

Product Identification

The complaint identifies Defendant’s "Next-Generation Firewalls," including but not limited to the PA-5220, PA-5250, PA-5260, PA-5280, and PA-5450 series, as well as the PA-5410, PA-5420, PA-5430, and PA-5440 series (collectively, the "Accused Products"). (Compl. ¶9, ¶19).

Functionality and Market Context

The infringement allegations are not directed at the firewall functionality itself, but rather at the underlying operation of the CPUs incorporated within these products. (Compl. ¶9, ¶19, ¶29, ¶39). The complaint specifies that the Accused Products use certain Intel-based CPUs (Haswell, Skylake, and newer architectures) and AMD-based CPUs (Zen, EPYC architectures). (Compl. ¶9, ¶19, ¶29, ¶39). The accused functionality is alleged to reside in the micro-architectural features of these CPUs related to interrupt management, cache coherency, and instruction processing. The complaint alleges that Defendant advertises the benefits of these processors in its marketing materials. (Compl. ¶12).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits that purportedly compare the asserted claims to the Accused Products. (Compl. ¶10, ¶20, ¶30, ¶40). The following summarizes the narrative infringement theories for the lead patents.

’626 and ’870 Patents Infringement Theory

The complaint alleges that the Accused Products, by incorporating and using the specified Intel and AMD CPUs, directly infringe the methods claimed in the ’626 and ’870 patents. (Compl. ¶9, ¶19). The core of the allegation is that the CPUs’ architectures for handling hardware interrupts in virtualized environments—specifically how they use on-core registers to evaluate partition ownership and priority levels to block or forward interrupts—practice the patented methods. (Compl. ¶10, ¶20).

Identified Points of Contention

  • Scope Questions: A central question will be whether the architectural components in the accused Intel and AMD CPUs (e.g., registers related to Intel's VT-x or AMD's AMD-V virtualization technologies) meet the specific definitions of "special purpose registers" and "partition identifier" as used in the patents. The dispute may focus on whether these terms are limited to the specific embodiments shown in the patents or can be construed to cover the commercial implementations developed independently by the CPU manufacturers.
  • Technical Questions: What public or reverse-engineered evidence will Plaintiff present to demonstrate that the accused CPUs perform the specific sequence of steps recited in the method claims? For example, for the ’870 Patent, what is the evidence that the accused CPU "compares" an incoming interrupt's partition identifier to a "stored partition identifier retrieved from" an on-core register to select a priority level for comparison, as the claim requires?

V. Key Claim Terms for Construction

The Term: "interrupt package" (from claim 1 of the ’971 Patent)

Context and Importance

The definition of this term is fundamental to the infringement analysis for the interrupt-related patents. The claim requires this "package" to include five distinct informational components. Practitioners may focus on this term because Defendant will likely argue for a narrow construction requiring a specific, contiguous data structure that may not exist in the accused systems, while Plaintiff may argue for a functional definition covering any transmission where the required information is conveyed to the processor, regardless of format.

Intrinsic Evidence for Interpretation

  • Evidence for a Broader Interpretation: The specification describes conveying "interrupt context information" generally, which may support an interpretation focused on the informational content rather than a rigid structural format. (’971 Patent, col. 2:28-34).
  • Evidence for a Narrower Interpretation: The claim explicitly recites a list of components comprising the package. The patent's Figure 3 depicts these components as distinct signals (131-136), which could be used to argue that the term requires a set of concurrently transmitted, discrete data elements.

The Term: "special purpose registers at the processor" (from claim 1 of the ’870 Patent)

Context and Importance

The inventive concept of the ’870 Patent appears to rest on moving interrupt blocking logic to such registers on the processor core. The case may turn on whether the control registers within the accused Intel and AMD CPUs, which manage virtualization and interrupt masking, qualify as the claimed "special purpose registers" used for "partition-based" blocking.

Intrinsic Evidence for Interpretation

  • Evidence for a Broader Interpretation: The specification describes registers with names like "Guest Priority Blocking Register" and "VMM Priority Blocking Register," suggesting the "special purpose" is defined by the function performed—partition-based blocking—rather than requiring a register that has no other purpose. (’870 Patent, Fig. 2).
  • Evidence for a Narrower Interpretation: The use of the term "special purpose" could be argued to exclude general-purpose processor control registers that were part of a broader CPU design (e.g., for Intel VT-x) and not created specifically and solely for the patented method. The detailed descriptions of these specific registers could be used to narrow the term's scope to structures with identical features.

VI. Other Allegations

Indirect Infringement

The complaint alleges induced infringement, stating that Defendant provides customers with user manuals and online instructions that encourage and instruct them to set up and configure the Accused Products in ways that infringe. (Compl. ¶12, ¶22, ¶32, ¶42). It also alleges contributory infringement on the basis that the accused CPU features are a material part of the patented inventions, are not staple articles of commerce suitable for non-infringing use, and are especially adapted to infringe. (Compl. ¶13, ¶23, ¶33, ¶43).

Willful Infringement

Willfulness is alleged based on Defendant’s continued infringement after receiving knowledge of the patents and the alleged infringement, at least as of the service of the complaint and its attached claim charts. (Compl. ¶12, ¶22, ¶32, ¶42). The prayer for relief requests a finding that the case is "exceptional" under 35 U.S.C. § 285, which could entitle Plaintiff to enhanced damages and attorneys' fees. (Compl., Prayer for Relief ¶e).

VII. Analyst’s Conclusion: Key Questions for the Case

  • Architectural Equivalence: A core technical question will be whether the specific micro-architectural implementations for managing interrupts and caching in commercial CPUs designed by Intel and AMD can be shown to operate in a manner that meets the limitations of the asserted claims. The dispute will likely involve a highly technical comparison of the patents' teachings against the actual operation of the accused processors.
  • Definitional Scope: The outcome may depend heavily on claim construction, particularly for terms like "interrupt package" and "special purpose registers." The key question for the court will be whether these terms should be interpreted broadly to cover the functionality found in the accused CPUs, or narrowly limited to the specific structures and embodiments disclosed in the patents.
  • Knowledge and Intent for Indirect Infringement: Given that the allegedly infringing technology resides deep within third-party components, a central question for the indirect infringement claims will be Plaintiff’s ability to prove Defendant’s state of mind. Can Plaintiff establish that Defendant, as a system integrator packaging the CPUs, knew or was willfully blind to the specific internal operations of those CPUs and intended its customers to use them in an infringing way?