Eire Og Innovations Ltd v. Palo Alto Networks Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Eire Og Innovations Limited (Ireland)
  • Defendant: Palo Alto Networks, Inc. (Delaware)
  • Plaintiff’s Counsel: BC LAW GROUP, Group
• Case Identification: 2:24-cv-00227, E.D. Tex., 04/03/2024
• Venue Allegations: Plaintiff alleges venue is proper because Defendant is registered to do business in Texas, has transacted business in the district, and maintains a regular and established place of business in Plano, Texas, within the district.
• Core Dispute: Plaintiff alleges that Defendant’s Next-Generation Firewall products, which incorporate specific Intel and AMD central processing units (CPUs), infringe four patents related to processor interrupt management and data caching techniques.
• Technical Context: The patents address low-level processor architecture for managing tasks in multi-core and virtualized environments, which is fundamental to the performance of high-throughput computing devices.
• Key Procedural History: The complaint alleges that Defendant has had knowledge of the asserted patents and their infringement at least as of the filing and service of the complaint, which included infringement claim charts for each patent.

Case Timeline

Date	Event
2009-05-07	U.S. Patent No. 8,117,399 Priority Date
2010-09-21	U.S. Patent No. 8,504,777 Priority Date
2012-02-14	U.S. Patent No. 8,117,399 Issued
2012-08-09	U.S. Patent No. 9,436,626 Priority Date
2012-08-09	U.S. Patent No. 9,442,870 Priority Date
2013-08-06	U.S. Patent No. 8,504,777 Issued
2016-09-06	U.S. Patent No. 9,436,626 Issued
2016-09-13	U.S. Patent No. 9,442,870 Issued
2024-04-03	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - “Processor interrupt interface with interrupt partitioning and virtualization enhancements,” Issued September 6, 2016

The Invention Explained

• Problem Addressed: In data processing systems with multiple processors or virtualized partitions, managing interrupt requests from a central controller can cause delays and software complexity, particularly when an interrupt is directed to a partition that is not currently active (Compl. ¶8; ’626 Patent, col. 1:11-34).
• The Patented Solution: The invention describes a processor-based interrupt management system where interrupt "context information"—including a partition identifier, priority level, and thread identifier—is sent directly to the target processor core over a shared interface. The processor core itself uses special purpose registers to evaluate this information and determine whether to block the interrupt or forward it to the correct partition, reducing the need for intervention by a hypervisor or complex logic in the interrupt controller (’626 Patent, Abstract; col. 2:15-34).
• Technical Importance: This architecture aims to reduce latency and software overhead in virtualized, multi-threaded environments, which is critical for the performance of high-throughput systems (’626 Patent, col. 2:25-34).

Key Claims at a Glance

• The complaint asserts infringement of one or more claims, including exemplary independent claim 1 (Compl. ¶¶ 9-10).
• Independent claim 1 of the ’626 Patent requires:
  • Receiving, at a processor, an "interrupt package" that includes a first interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier.
  • Processing the interrupt package against one or more partitions by comparing the received priority value and partition identifier against a stored priority level and stored partition identifier retrieved from "special purpose registers at the processor."
  • Determining, on a partition basis, whether the interrupt request is blocked or forwarded to a targeted thread based on the comparison.
• The complaint does not explicitly reserve the right to assert dependent claims, but the general allegation of infringing "one or more claims" leaves this possibility open (Compl. ¶9).

U.S. Patent No. 9,442,870 - “Interrupt priority management using partition-based priority blocking processor registers,” Issued September 13, 2016

The Invention Explained

• Problem Addressed: Conventional systems that control interrupt priority blocking at the interrupt controller, rather than at the processor core, can create performance issues and access time penalties in partitioned or virtualized environments (’870 Patent, col. 1:12-24).
• The Patented Solution: The patent discloses moving the interrupt priority blocking logic onto the processor core itself through the use of "special purpose priority blocking registers." These on-core registers allow different partitions (e.g., a hypervisor and a guest operating system) to independently manage their own interrupt priority rules, for example by comparing an incoming interrupt's priority level to a stored threshold for that specific partition (’870 Patent, Abstract; col. 2:5-24).
• Technical Importance: This method provides for more efficient and granular control over interrupt handling in complex, multi-partition systems, thereby improving system responsiveness (’870 Patent, col. 2:1-10).

Key Claims at a Glance

• The complaint asserts infringement of one or more claims, including exemplary independent claim 1 (Compl. ¶¶ 19-20).
• Independent claim 1 of the ’870 Patent requires:
  • Receiving, at a processor, an "interrupt package" for a physical interrupt request, which includes a priority value and a partition identifier.
  • Processing the interrupt package by comparing the priority value and partition identifier against a stored priority level and stored partition identifier retrieved from "one or more special purpose registers at the processor."
  • Determining, on a partition basis, if the physical interrupt request is blocked or forwarded to a targeted virtual processor.
• The complaint’s allegation of infringing "one or more claims" suggests the right to assert other claims may be reserved (Compl. ¶19).

U.S. Patent No. 8,504,777 - “Data processor for processing decorated instructions with cache bypass,” Issued August 6, 2013

Technology Synopsis

The patent describes a system for maintaining data coherency when executing special "decorated instructions" that command an "intelligent memory" to perform an atomic operation, such as a read-modify-write. To prevent the processor from using stale data, if the decorated instruction includes a "cache bypass" flag, the corresponding cache entry in the processor is invalidated, and the operation is performed directly on the intelligent memory, ensuring data integrity (’777 Patent, Abstract; col. 2:48-67).

Asserted Claims

The complaint identifies exemplary independent claim 16 as infringed (Compl. ¶30).

Accused Features

The complaint accuses certain Intel-based (Skylake and newer) and AMD-based (EPYC) CPUs within Defendant’s firewall products of infringement (Compl. ¶29).

U.S. Patent No. 8,117,399 - “Processing of coherent and incoherent accesses at a uniform cache,” Issued February 14, 2012

Technology Synopsis

The patent discloses a method for managing a unified cache that stores both coherent information (e.g., shared data that must be kept consistent across cores) and incoherent information (e.g., non-modifiable instruction code). Each cache line is marked accordingly. A coherent read to an incoherent line is treated as a cache miss, forcing a query to main memory, while an incoherent read can hit on either type. This technique reduces unnecessary cache coherency traffic (snoops) on the system interconnect, which can improve overall performance (’399 Patent, Abstract; col. 2:1-10).

Asserted Claims

The complaint identifies exemplary independent claim 14 as infringed (Compl. ¶40).

Accused Features

The complaint accuses certain Intel-based (Skylake and newer) and AMD-based (EPYC) CPUs within Defendant’s firewall products of infringement (Compl. ¶39).

III. The Accused Instrumentality

Product Identification

The complaint identifies Defendant’s PA-5220, PA-5250, PA-5260, PA-5280, PA-5450, PA-5410, PA-5420, PA-5430, and PA-5440 Next-Generation Firewalls as the "Accused Products" (Compl. ¶¶ 9, 19, 29, 39).

Functionality and Market Context

The infringement allegations focus on the underlying CPUs used within these firewalls, specifically Intel-based CPUs with Haswell, Skylake, and newer architectures, and AMD-based CPUs with Zen and EPYC architectures (Compl. ¶¶ 9, 19, 29, 39). The complaint alleges that these CPUs incorporate the patented technologies for managing interrupts and cache coherency. It further alleges that Defendant advertises the benefits of these processors and provides customers with instructions and user manuals on how to configure and utilize the Accused Products in ways that use the infringing functionality (Compl. ¶¶ 12, 22, 32, 42). The complaint references a PA-5400 series firewall installation guide, which allegedly provides instructions on how to set up and utilize the accused products (Compl. ¶12).

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits that compare the asserted claims to the Accused Products. The following summarizes the infringement theories as described in the complaint's narrative.

• ’626 Patent and ’870 Patent Infringement Allegations:
  The complaint alleges that the Accused Products directly infringe at least claim 1 of the ’626 and ’870 patents because the Intel and AMD CPUs they contain perform the claimed methods for managing interrupts (Compl. ¶¶ 9-10, 19-20). The core of the allegation is that these CPUs receive interrupt requests containing partition and priority information and use dedicated on-core registers to manage interrupt blocking and routing on a per-partition basis, as required by the claims. The complaint cites Defendant’s promotional materials and user manuals as evidence that Defendant instructs its customers to use the firewalls in a manner that practices the claimed inventions (Compl. ¶¶ 12, 22).

Identified Points of Contention

• Scope Questions: The dispute may center on whether the architecture of the accused CPUs falls within the scope of the patent claims. For instance, a question for the court could be whether the interrupt handling mechanisms in Intel's and AMD's processors constitute an "interrupt package" as the term is used in the patents.
• Technical Questions: A key technical question is what evidence demonstrates that the accused CPUs perform the specific step of comparing a received "partition identifier" against a "stored partition identifier" retrieved from "special purpose registers" to determine interrupt blocking. The complaint's allegations will require detailed technical substantiation beyond the high-level documents cited.

V. Key Claim Terms for Construction

• The Term: "special purpose registers at the processor" (Asserted in claim 1 of the ’626 and ’870 patents).
• Context and Importance: This term is central to the asserted claims of the ’626 and ’870 patents, as the claimed point of novelty is moving interrupt management logic from a separate controller onto the processor core via these registers. The infringement analysis will depend heavily on whether the register architectures in the accused Intel and AMD CPUs (e.g., registers related to Intel's APIC or AMD's AVIC) are found to be "special purpose registers at the processor."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Plaintiff may argue that the term should be interpreted functionally to cover any on-core register that performs the claimed interrupt management tasks. The specification describes the registers in terms of their function, such as storing partition IDs and priority levels, which could support an argument that the term is not limited to a specific hardware implementation (’626 Patent, col. 2:46-59).
  • Evidence for a Narrower Interpretation: Defendant may argue for a narrower construction limited to the specific register embodiments disclosed, such as the "LPIDR", "INTLEVEL", "EPR", and "EPIDR" registers explicitly shown and described in the patent figures and detailed description (’626 Patent, Fig. 2; col. 5:3-13). This could support an argument that the accused CPUs, which use different register naming and architectures, do not meet this limitation.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all four asserted patents. The stated basis for inducement is that Defendant provides customers with "instructions and user manuals detailing how to setup, configure, and utilize the Accused Products to utilize the infringing functionality" (Compl. ¶¶ 12, 22, 32, 42).
• Willful Infringement: Willfulness is alleged based on knowledge obtained "At least as of the filing and service of this complaint," which included infringement claim charts for each asserted patent. The complaint further alleges that Defendant continues to infringe despite this knowledge, and that it acted "knowing and intending (or with willful blindness to the fact)" that its customers would commit infringing acts (Compl. ¶¶ 12, 22, 32, 42).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of claim construction: Can the term "special purpose registers at the processor," as defined in the context of the patents’ specific embodiments, be construed to read on the register architectures implemented in the accused commercial CPUs from Intel and AMD? The viability of the infringement claims for the ’626 and ’870 patents will likely depend on the answer.
• A second central issue will be one of technical evidence: Beyond the high-level product documents cited in the complaint, what technical proof can Plaintiff provide to show that the accused CPUs perform the precise, multi-step methods of interrupt and cache management required by the asserted claims? The case will likely require a deep dive into the micro-architectural operations of the accused processors.
• A third question relates to the allegations concerning the ’777 and ’399 patents: Can Plaintiff demonstrate that the accused CPUs' cache bypass and coherency mechanisms map onto the specific claim limitations related to "decorated instructions" and the handling of "incoherent" versus "coherent" cache lines, or will Defendant be able to establish a fundamental operational mismatch between its products and the patented methods?