DCT

2:24-cv-00235

Daedalus Prime LLC v. MediaTek Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:24-cv-00235, E.D. Tex., 04/08/2024
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation subject to personal jurisdiction in the district and has committed acts of infringement there. Plaintiff further alleges Defendant maintains physical facilities and employees in Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s semiconductor chips, particularly its Dimensity line of System-on-a-Chip (SoC) products, infringe eight U.S. patents related to microprocessor power management, multi-core architecture, cache coherency, and hardware security.
  • Technical Context: The technologies at issue concern fundamental aspects of modern multi-core processor design, focusing on methods to enhance performance and energy efficiency while ensuring secure operation in devices like smartphones and computers.
  • Key Procedural History: The complaint alleges that Defendant has had knowledge of all eight asserted patents since at least August 23, 2022, based on their assertion in prior litigation filed by the Plaintiff against a third party, which forms the basis for the willfulness allegations.

Case Timeline

Date Event
2010-11-30 U.S. Patent No. 8,769,316 Priority Date
2011-01-04 U.S. Patent No. 8,984,228 Priority Date
2011-12-15 U.S. Patent No. 10,372,197 Priority Date
2011-12-15 U.S. Patent No. 9,887,838 Priority Date
2011-12-22 U.S. Patent No. 10,740,281 Priority Date
2012-12-28 U.S. Patent No. 10,705,960 Priority Date
2012-12-28 U.S. Patent No. 10,725,919 Priority Date
2013-03-11 U.S. Patent No. 11,507,167 Priority Date
2014-07-01 U.S. Patent No. 8,769,316 Issue Date
2015-03-17 U.S. Patent No. 8,984,228 Issue Date
2018-02-06 U.S. Patent No. 9,887,838 Issue Date
2019-08-06 U.S. Patent No. 10,372,197 Issue Date
2020-07-07 U.S. Patent No. 10,705,960 Issue Date
2020-07-28 U.S. Patent No. 10,725,919 Issue Date
2020-08-11 U.S. Patent No. 10,740,281 Issue Date
2022-08-23 Alleged Knowledge of All Asserted Patents by Defendant
2022-11-22 U.S. Patent No. 11,507,167 Issue Date
2024-04-08 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,769,316 - "Dynamically Allocating a Power Budget Over Multiple Domains of a Processor"

  • Issued: July 1, 2014
  • The Invention Explained:
    • Problem Addressed: The patent describes that as processors integrated multiple types of circuitry (e.g., CPU cores, graphics), these different "domains" consume varying amounts of power, but "suitable mechanisms to ensure that these different units have sufficient power do not presently exist" (’316 Patent, col. 1:18-22).
    • The Patented Solution: The invention discloses a method where a power controller determines a total power budget for a processor and dynamically allocates portions of that budget to different domains, such as a CPU domain and a GPU domain. This allocation involves providing a "minimum reservation value" to each domain and then sharing the remaining budget based on "sharing policy value[s]" for each domain (’316 Patent, Cl. 8). The power sharing logic performs "dynamic control and re-allocation of an available power budget between multiple independent domains" (’316 Patent, col. 8:33-36, citing Fig. 6).
    • Technical Importance: This approach enables intelligent, real-time power distribution within a System-on-a-Chip (SoC), optimizing performance and efficiency under a shared thermal or power limit (Compl. ¶15).
  • Key Claims at a Glance:
    • The complaint asserts independent method Claim 8 (Compl. ¶54).
    • Essential elements of Claim 8 include:
      • Determining, in a power controller of a multi-domain processor, a power budget for the processor for a current time interval.
      • Determining, in the power controller, a portion of the power budget to be allocated to first and second domains.
      • This determination includes allocating a minimum reservation value to the first domain and a minimum reservation value to the second domain.
      • It also includes sharing a remaining portion of the power budget according to a first sharing policy value for the first domain and a second sharing policy value for the second domain.
      • Controlling a frequency of the first and second domains based on the allocated portions.
    • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 10,372,197 - "User Level Control of Power Management Policies"

  • Issued: August 6, 2019
  • The Invention Explained:
    • Problem Addressed: The patent notes the complexity involved in tuning the many power management features of a modern processor, stating that "end users rarely venture into tuning individual features for their target usage, and thus the potential benefit of the features are often not realized" (’197 Patent, col. 2:5-8).
    • The Patented Solution: The invention proposes a simplified control mechanism called an "energy performance bias" (EPB). A user or operating system provides a single EPB value that represents a desired trade-off between power and performance. A "power control unit" then uses this EPB value to access a "power/performance table" and, based on the information in the table, updates the settings for multiple power management features simultaneously (’197 Patent, Abstract; col. 7:55-8:4, citing Fig. 4).
    • Technical Importance: This technology simplifies complex power management decisions into a single, high-level policy choice, making it easier to optimize processor behavior for different use cases without requiring expert knowledge of low-level hardware settings (Compl. ¶20).
  • Key Claims at a Glance:
    • The complaint asserts independent apparatus Claim 1 (Compl. ¶73).
    • Essential elements of Claim 1 include:
      • A processor comprising a plurality of cores, a cache memory, and an interconnect.
      • A power controller to control a plurality of power management features of the processor.
      • The power controller includes a tuning circuit configured to:
        • receive a workload configuration input regarding a workload;
        • receive a plurality of energy performance bias (EPB) values and determine a global EPB value based thereon; and
        • update at least one setting of at least one of the power management features based on the workload configuration input and the global EPB value.
    • The complaint does not explicitly reserve the right to assert dependent claims.

Other Asserted Patents

  • Patent Identification: U.S. Patent No. 10,740,281, "Asymmetric Performance Multicore Architecture with Same Instruction Set Architecture," issued August 11, 2020.

  • Technology Synopsis: The patent addresses processor design by using a mix of high-performance, high-power cores and lower-performance, lower-power cores that all support the same instruction set (’281 Patent, Abstract; Compl. ¶25). This "asymmetric" or "heterogeneous" approach allows an operating system to control the core mix, activating more powerful cores for demanding tasks and more efficient cores for background tasks to save power (’281 Patent, Cl. 8).

  • Asserted Claims: At least Claim 8 (method) is asserted (Compl. ¶98).

  • Accused Features: The complaint alleges that MediaTek's Dimensity 9000 SoCs, which include a mix of higher-performance Cortex-A710 cores and lower-power, high-efficiency Cortex-A510 cores, infringe the ’281 Patent (Compl. ¶101, ¶105).

  • Patent Identification: U.S. Patent No. 8,984,228, "Providing Common Caching Agent for Core and Integrated Input/Output (IO) Module," issued March 17, 2015.

  • Technology Synopsis: The patent addresses the problem of maintaining cache coherency when an Input/Output (IO) component is integrated onto the same chip as a multiprocessor (’228 Patent, col. 1:19-25). The solution is an apparatus with a single, distributed "caching agent" that performs cache coherency operations for both the processor cores and the integrated IO (IIO) module, which is alleged to reduce snoop traffic and improve efficiency (’228 Patent, Abstract; Compl. ¶30-31).

  • Asserted Claims: At least Claims 1 and 11 (apparatus) are asserted (Compl. ¶127).

  • Accused Features: The complaint alleges that the ARM DynamIQ Shared Unit-110 (DSU-110) in Dimensity 9000 SoCs functions as the claimed single, distributed caching agent for both the processor cores and IO interfaces (Compl. ¶133, ¶136-137).

  • Patent Identification: U.S. Patent No. 11,507,167, "Controlling Operating Voltage of a Processor," issued November 22, 2022.

  • Technology Synopsis: The patent describes a method for managing voltage transitions to reduce latency when a processor core exits a low-power state (’167 Patent, col. 2:28-46). When a first core requests a higher voltage, the power controller first causes a voltage regulator to increase the voltage to an interim "safe" level. This interim level is sufficient to allow a second, inactive core to wake up quickly, after which the voltage increase for the first core is completed (’167 Patent, Abstract; Compl. ¶35).

  • Asserted Claims: At least Claim 1 (apparatus) is asserted (Compl. ¶151).

  • Accused Features: The complaint alleges that Dimensity 9000 SoCs, with their Dynamic Voltage and Frequency Scaling (DVFS) circuitry and Energy Aware Scheduler, are capable of performing the claimed multi-step voltage transitions to manage core active/inactive states (Compl. ¶158, ¶164, ¶168).

  • Patent Identification: U.S. Patent No. 9,887,838, "Method and Device for Secure Communications Over a Network Using a Hardware Security Engine," issued February 6, 2018.

  • Technology Synopsis: The patent describes a method for establishing a secure communication session using a hardware security engine on a client device's SoC that is separate from the main processor core (’838 Patent, col. 4:17-19). This engine generates random nonces, performs cryptographic key exchanges, and stores session keys in a secure memory, using a security key encoded during manufacturing, to protect sensitive operations from the main processor environment (’838 Patent, Abstract; Compl. ¶40-41).

  • Asserted Claims: At least Claim 9 (method) is asserted (Compl. ¶182).

  • Accused Features: The complaint alleges that MediaTek’s CryptoCore cryptographic module, a sub-chip separate from the main processor core in products like the Dimensity 9200, functions as the claimed security engine. It is alleged to perform the claimed steps of generating nonces for TLS handshakes, managing key exchanges, and using keys encoded into One Time Programmable memory during manufacturing (Compl. ¶185, ¶187, ¶190).

  • Patent Identification: U.S. Patent Nos. 10,705,960 and 10,725,919, both titled "Processors Having Virtually Clustered Cores and Cache Slices," issued July 7, 2020 and July 28, 2020, respectively.

  • Technology Synopsis: These related patents address performance bottlenecks in many-core processors, such as increased cache latency and lower memory bandwidth, by creating "virtual clusters" of cores and their associated distributed cache slices (’960 Patent, col. 1:32-47). This architecture provides coherent, non-uniform access to the cache and allows power and frequency to be controlled on a per-cluster basis, which is intended to improve memory bandwidth and efficiency (’960 Patent, Abstract; Cl. 15).

  • Asserted Claims: At least Claim 15 of the ’960 Patent (method) and Claim 16 of the ’919 Patent (method) are asserted (Compl. ¶217, ¶258).

  • Accused Features: The complaint alleges that Dimensity 9000 SoCs, which group ARM cores into distinct clusters (e.g., Cortex-A510 clusters and Cortex-A710 clusters) that are managed by a DynamIQ Shared Unit, implement the claimed virtual clustering, non-uniform cache access, and cluster-based power gating (Compl. ¶220, ¶231, ¶235, ¶238).

III. The Accused Instrumentality

  • Product Identification: The complaint names specific MediaTek products including the Dimensity 9300, 9200, and 9000 series SoCs, the Kompanio 1380 Chromebook chip, and the Dimensity Auto Cockpit CX-1 automotive chip (Compl. ¶7). The infringement allegations focus primarily on processors based on the ARMv8.2 and ARMv9 architectures, with the Dimensity 9300 and 9000 SoCs serving as the primary examples (Compl. ¶51).
  • Functionality and Market Context: The accused products are highly integrated SoCs that serve as the central processors for smartphones and other consumer electronics (Compl. ¶12). Their relevant functionality, as described in the complaint, includes multi-domain power management through "Intelligent Power Allocation" (IPA) technology, which dynamically allocates a power budget between CPU and GPU domains (Compl. ¶59). They employ heterogeneous multi-core architectures, combining high-performance and high-efficiency cores (e.g., Cortex-X4, A720, A510) organized into clusters (Compl. ¶76, ¶101). These clusters are interconnected with a shared L3 cache via a DynamIQ Shared Unit (DSU) that manages cache coherency (Compl. ¶80, ¶109). The SoCs also contain dedicated hardware security modules, such as the "CryptoCore" module, for handling cryptographic operations separately from the main CPU cores (Compl. ¶185). The complaint positions MediaTek as the world's 5th largest fabless semiconductor company, powering over 2 billion devices annually (Compl. ¶50).

IV. Analysis of Infringement Allegations

8,769,316 Patent Infringement Allegations

Claim Element (from Independent Claim 8) Alleged Infringing Functionality Complaint Citation Patent Citation
determining, in a power controller of a multi-domain processor, a power budget for the multi-domain processor for a current time interval... The Dimensity 9300 includes a Power Controller that determines a power budget for its multi-domain (CPU and GPU) processor for a current time interval. ¶57 col. 2:4-7
determining, in the power controller, a portion of the power budget to be allocated to the first and second domains, including allocating a minimum reservation value to the first domain and a minimum reservation value to the second domain... The Dimensity 9300's Intelligent Power Allocation (IPA) dynamically allocates the power budget. The complaint alleges this provides "guaranteed minimum performance," which corresponds to the "minimum reservation value." A diagram of the IPA thermal management approach is provided as evidence (Compl. p. 24). ¶58, ¶59 col. 2:8-13
...and sharing a remaining portion of the power budget according to a first sharing policy value for the first domain and a second sharing policy value for the second domain... The accused IPA policy allocates extra power between the CPU and GPU domains "based on the weight for each device," which is alleged to constitute the claimed sharing based on policy values. ¶59 col. 2:13-16
controlling a frequency of the first domain and a frequency of the second domain based on the allocated portions. The complaint alleges that by allocating power to the CPU and GPU domains via the IPA system, the accused products inherently control the performance level and thus the operating frequency of those domains. ¶55, ¶59 col. 2:17-19
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the accused IPA system's "guaranteed minimum performance" (Compl. p. 24) constitutes "allocating a minimum reservation value" as required by the claim. A defendant could argue that its dynamic allocation policy is technically distinct from a fixed "reservation." Similarly, whether allocating extra power "based on the weight for each device" meets the "sharing policy value" limitation will likely be a point of dispute.
    • Technical Questions: The complaint relies on marketing materials and a high-level technical diagram to describe the IPA system's functionality (Compl. p. 24). A key technical question will be what evidence demonstrates that this system actually performs the specific two-part allocation required by the claim: first setting a minimum reservation, and then sharing the remainder.

10,372,197 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A processor comprising: a plurality of cores; a cache memory; an interconnect to couple the plurality of cores and the cache memory... The Dimensity 9300 SoC contains a plurality of cores (four Cortex-X4 and four Cortex-A720) (¶76), L1 and L2 cache memories (¶78), and a DynamIQ Shared Unit (DSU) that serves as an interconnect coupling the cores to L3 cache memory (¶80). Diagrams of core components are provided as evidence (Compl. p. 30). ¶74-80 col. 6:61-67
...and a power controller to control a plurality of power management features of the processor... The accused SoCs include logic such as ARM Power Policy Units configured by an ARM System Control Processor to control power management features. ¶82 col. 7:1-4
...wherein the power controller includes a tuning circuit to receive a workload configuration input regarding a workload, receive a plurality of energy performance bias (EPB) values and determine a global EPB value based thereon... The complaint alleges that ARM's Intelligent Power Allocation (IPA) logic functions as the claimed tuning circuit. It is alleged to receive "real-time CPU and GPU performance requests" which correspond to the claimed "workload configuration input" and "EPB values." A diagram showing the IPA control algorithm is provided as evidence (Compl. p. 32). ¶83, ¶84 col. 7:5-11
...and update at least one setting of at least one of the plurality of power management features based on the workload configuration input and the global EPB value. The IPA logic is alleged to use the performance requests and power models to "cause settings of Power Policy Units to be updated to maximize requested performance without exceeding the Thermal Design Power for the SoC." ¶84 col. 7:11-14
  • Identified Points of Contention:
    • Scope Questions: The dispute may center on whether the accused IPA's "real-time CPU and GPU performance requests" (Compl. ¶84) can be construed as the claimed "workload configuration input" and "energy performance bias (EPB) values." A defendant might argue that the patent describes a more explicit, user- or OS-set policy value, whereas the accused system uses real-time, algorithmic performance targets.
    • Technical Questions: The complaint maps the accused "Intelligent Power Allocation logic" to the claimed "tuning circuit." A technical question for the court will be whether the evidence shows that the IPA system operates in the manner claimed—specifically, by receiving distinct EPB values and using them to determine a global value to update settings, as opposed to operating as an integrated, real-time feedback loop.

V. Key Claim Terms for Construction

  • Term (’316 Patent): "minimum reservation value"
  • Context and Importance: Infringement of Claim 8 hinges on whether the accused IPA system's function of providing "guaranteed minimum performance" (Compl. p. 24) satisfies this limitation. The definition will determine if a dynamic performance floor is equivalent to a reserved portion of a power budget. Practitioners may focus on this term because it distinguishes a simple proportional sharing scheme from the two-step allocation method recited in the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the concept broadly as ensuring a "minimum power level" for a domain, which could support an argument that any mechanism guaranteeing a performance floor meets the limitation (’316 Patent, col. 4:51-52).
    • Evidence for a Narrower Interpretation: The patent also describes these values as being "programmed via software into one or more registers," which may suggest they are pre-configured or semi-static values rather than the output of a fully dynamic, real-time algorithm (’316 Patent, col. 4:47-49).
  • Term (’197 Patent): "energy performance bias (EPB) value"
  • Context and Importance: The infringement theory equates the accused products' "real-time CPU and GPU performance requests" with the claimed "EPB values" (Compl. ¶84). The construction of this term will be critical to determining if a dynamic performance target from a scheduler is the same as the user- or OS-level policy input described in the patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent abstract describes the EPB value simply as input used to access a tuning table. The detailed description characterizes it as a "simple high level input from an end user to indicate a power/performance tradeoff preference," which could be argued to encompass automated performance requests from system software (’197 Patent, Abstract; col. 2:35-39).
    • Evidence for a Narrower Interpretation: The specification consistently describes the EPB value as a single, user-settable parameter that is resolved into a "global EPB value" and used to look up settings in a pre-tuned "Power/Performance Table" (’197 Patent, Fig. 1; col. 7:55-8:4). This could support a narrower construction that requires a discrete policy value rather than a continuous stream of performance targets.

VI. Other Allegations

  • Indirect Infringement: For each asserted patent, the complaint alleges that MediaTek induces infringement by supplying the accused SoCs to consumers and instructing them to use the products in their ordinary, infringing manner (e.g., Compl. ¶61-62). It further alleges contributory infringement, stating the accused products are a material part of the invention and are not staple articles of commerce suitable for substantial non-infringing use (e.g., Compl. ¶63).
  • Willful Infringement: The complaint asserts willful infringement for all patents based on alleged knowledge of the patents since at least August 23, 2022. This date corresponds to the filing of a separate lawsuit by Daedalus v. Mazda Motor Corp. asserting the same patents, which allegedly put MediaTek on notice (e.g., Compl. ¶68, ¶93, ¶122).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of technical equivalence: Does MediaTek's dynamic, algorithm-based "Intelligent Power Allocation" system, which responds to real-time performance requests, operate in a manner that is functionally equivalent to the more discrete, table-based power management systems described and claimed in the '316 and '197 patents?
  • A key question of claim scope will be whether terms rooted in the patents' specific embodiments, such as "minimum reservation value" ('316 Patent) and "energy performance bias (EPB) value" ('197 Patent), can be construed broadly enough to encompass the functionalities of the accused products' real-time performance and thermal management systems.
  • A central architectural question for the full suite of patents will be whether MediaTek's implementation of industry-standard ARM architectures (e.g., big.LITTLE core configurations, DynamIQ Shared Units, and CryptoCore security modules) infringes the specific methods and apparatuses claimed by these former Intel-invented patents, or if those implementations are technically distinct.