DCT
2:24-cv-00238
Monterey Research LLC v. Renesas Electronics Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Monterey Research, LLC (Delaware)
- Defendant: Renesas Electronics Corporation (Japan); Denso Corporation (Japan); Denso International America, Inc. (Delaware)
- Plaintiff’s Counsel: Russ August & Kabat
- Case Identification: 2:24-cv-00238, E.D. Tex., 04/10/2024
- Venue Allegations: Plaintiff alleges venue is proper for foreign defendants Renesas and Denso in any judicial district. Venue is alleged to be proper for Denso International America, Inc. based on its maintenance of regular and established places of business within the Eastern District of Texas, including facilities in Plano and McAllen.
- Core Dispute: Plaintiff alleges that Defendants’ semiconductor products, including microcontrollers and devices with embedded flash memory used in the automotive sector, infringe four U.S. patents related to memory cell erasing methods, system-level reset functions, and mixed-signal processor architectures.
- Technical Context: The patents-in-suit address fundamental technologies in semiconductor design, including the efficiency of non-volatile memory operations, the reliability of device startup procedures, and the integration of analog and digital components on a single chip.
- Key Procedural History: The complaint alleges a multi-year history of pre-suit communications, beginning in 2017, in which Plaintiff notified Defendant Renesas of the asserted patents and its infringement allegations. These communications allegedly included in-person meetings and the presentation of claim charts for U.S. Patent Nos. 7,679,968 and 6,243,300. Plaintiff also alleges it notified Defendant Denso and its customers, including Toyota and Honda, of the alleged infringement.
Case Timeline
| Date | Event |
|---|---|
| 2000-02-16 | ’300 Patent Priority Date |
| 2000-10-26 | ’688 Patent Priority Date |
| 2001-06-05 | ’300 Patent Issue Date |
| 2003-09-16 | ’133 Patent Priority Date |
| 2006-08-08 | ’133 Patent Issue Date |
| 2007-05-29 | ’968 Patent Priority Date |
| 2010-03-16 | ’968 Patent Issue Date |
| 2010-11-02 | ’688 Patent Issue Date |
| 2017-10-25 | Renesas allegedly presented with claim chart for ’968 Patent |
| 2017-12-20 | Renesas allegedly presented with claim chart for ’300 Patent |
| 2018-08-07 | Renesas allegedly notified of infringement of ’300 and ’968 Patents |
| 2018-09-11 | Denso allegedly notified of infringement of ’300 and ’968 Patents |
| 2022-03-01 | Renesas allegedly notified of infringement of ’133 and ’688 Patents |
| 2024-04-10 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,243,300 - “Substrate Hole Injection for Neutralizing Spillover Charge Generated During Programming of a Non-Volatile Memory Cell”
The Invention Explained
- Problem Addressed: The patent’s background section describes that conventional methods for erasing non-volatile memory cells can be slow. This is attributed in part to carriers generated through "band-to-band tunneling" that can limit the effectiveness of the "hot carriers" used in the erasure process (’300 Patent, col. 2:1-4).
- The Patented Solution: The invention proposes a method for erasing a memory cell that involves generating "neutralizing holes" in the substrate and moving them into the memory cell's channel (’300 Patent, Abstract). These holes are intended to neutralize "spillover electrons" that can accumulate during operation, thereby preventing degradation of the cell's programmed threshold voltage and improving erase efficiency (’300 Patent, col. 2:13-15). Figure 6A illustrates the concept of "spillover electrons" and the generation of neutralizing "holes" (’300 Patent, Fig. 6A).
- Technical Importance: The described method was intended to provide a more efficient and reliable way to erase non-volatile memory cells, a core operation for technologies like flash memory (’300 Patent, col. 2:1-4).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶30).
- The essential elements of claim 1 are:
- A method of erasing a memory cell that has spillover electrons, comprising:
- generating neutralizing holes in said substrate;
- moving said neutralizing holes to said channel; and
- substantially neutralizing said spillover electrons with said neutralizing holes moved to said channel.
- The complaint does not explicitly reserve the right to assert dependent claims for the ’300 Patent.
U.S. Patent No. 7,679,968 - “Enhanced Erasing Operation for Non-Volatile Memory”
The Invention Explained
- Problem Addressed: The patent describes how, during an erasing operation, capacitive coupling between the memory cell's well and its word line can cause the word line voltage to rise undesirably (’968 Patent, col. 2:1-4). This disruption can "delay and/or disrupt the erasing operation of the memory cell" (’968 Patent, col. 2:10-11).
- The Patented Solution: The invention discloses a method and device architecture that introduces a "timing gap" between the application of voltages to the word line and the well (’968 Patent, Abstract). A negative voltage is first applied to the word line; only "when the negative voltage reaches a predetermined voltage" is a positive voltage then applied to the well (’968 Patent, Abstract). This sequencing is designed to mitigate the disruptive effects of capacitive coupling (’968 Patent, col. 2:36-41).
- Technical Importance: This timed voltage application enables a "faster and more effective erasing operation" by ensuring that the necessary electrical potentials are established and maintained without interference from parasitic capacitance (’968 Patent, col. 2:40-41).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶41).
- The essential elements of claim 1 are:
- A semiconductor device comprising:
- a memory cell array having a plurality of non-volatile memory cells;
- a negative voltage generating circuit for applying a negative voltage to a word line during an erasing operation; and
- a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage, wherein there is a timing gap between the start of applying the negative voltage and the start of applying the positive voltage.
- The complaint does not explicitly reserve the right to assert dependent claims for the ’968 Patent.
U.S. Patent No. 7,089,133 - “Method and Circuit for Providing a System Level Reset Function For an Electronic Device”
Technology Synopsis
The patent addresses imprecision in conventional power-on reset circuits, which can lead to data corruption or malfunction if a device operates under low voltage conditions (Compl. ¶50). The invention teaches a tiered reset system that combines an initial, less-precise reset function for low-voltage power-on conditions with a subsequent, tunable reset function that offers higher precision after the device is properly powered and calibrated, thereby increasing operational reliability (Compl. ¶51).
Asserted Claims & Accused Features
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶53).
- Accused Features: The accused features are the power-on reset circuits in Renesas microcontrollers (e.g., M16C, RA6, RX, and RL series), which are alleged to perform a multi-stage reset process involving an initial reset, a tunable Low Voltage Detection (LVD) reset, and a precision reset based on verified calibration data (Compl. ¶¶52-53).
U.S. Patent No. 7,825,688 - “Programmable Microcontroller Architecture (Mixed Analog/Digital)”
Technology Synopsis
The patent addresses limitations of prior microcontrollers that could not integrate different types of programmable analog circuits (e.g., Continuous Time and Switched Capacitor) with digital circuits on a single semiconductor device (Compl. ¶62). The invention describes a programmable System-on-a-Chip architecture featuring both programmable analog and digital blocks interconnected by a programmable structure, allowing for dynamic, on-the-fly reconfiguration (Compl. ¶63; ’688 Patent, col. 2:7-13).
Asserted Claims & Accused Features
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶65).
- Accused Features: The accused products (e.g., Renesas RH850 Microcontrollers) are alleged to infringe by incorporating analog circuit blocks (A/D converter), digital circuit blocks (Clocked Serial Interface), a bus (P-Bus) connecting these blocks, and a clock to control the data coupling to the bus (Compl. ¶65).
III. The Accused Instrumentality
Product Identification
- The complaint identifies several categories of accused products, all manufactured by Renesas and incorporated into products by Denso and DIA. These include:
- For the ’300 and ’968 Patents: Renesas products with embedded flash memory made using 28 nm, 40 nm, and 90 nm processes, with the Renesas RH850 and RX600 families cited as examples (Compl. ¶¶29, 30, 40, 41).
- For the ’133 Patent: Renesas M16C, RA 6 Series, RX, and RL series microcontrollers (Compl. ¶52).
- For the ’688 Patent: Renesas RH850 family microcontrollers (Compl. ¶64).
Functionality and Market Context
- The accused products are semiconductor devices, primarily microcontrollers and integrated circuits designed and marketed for automotive applications (Compl. ¶23).
- Defendant Denso is described as a customer of Renesas that integrates these semiconductor devices into a wide variety of automotive components, from engine control units to in-cabin information and display systems for leading auto manufacturers (Compl. ¶22).
IV. Analysis of Infringement Allegations
6,243,300 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| generating neutralizing holes in said substrate; | Holes are generated by applying a large positive pulse to the source line for the memory cell. | ¶30 | col. 12:4-11 |
| moving said neutralizing holes to said channel; | The neutralizing holes move to the channel in response to the large negative voltage on the memory gate. | ¶30 | col. 12:60-65 |
| and substantially neutralizing said spillover electrons with the neutralizing holes moved to said channel. | The neutralizing holes neutralize the spillover electrons in the channel. | ¶30 | col. 13:3-5 |
- Identified Points of Contention:
- Technical Questions: A primary factual question may be whether the accused devices' memory cells generate "spillover electrons" as described in the patent, and whether the accused erasing method functions to "substantially neutralize" them. The complaint describes the accused method but does not provide technical evidence demonstrating the presence of this specific phenomenon in the accused products.
- Scope Questions: The interpretation of "spillover electrons" may be a point of contention. The patent specification illustrates this concept in the context of a two-bit memory cell where programming one bit affects the adjacent region (’300 Patent, Fig. 6A). Whether this term can be construed to cover other charge-related phenomena in the accused single-bit or multi-bit memory cells will raise a claim construction question.
7,679,968 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A memory cell array having a plurality of non-volatile memory cells. | The accused products include non-volatile flash memory devices with multiple memory cells. | ¶41a | col. 1:21-24 |
| A negative voltage generating circuit for applying a negative voltage to a word line... | The accused products include a circuit that generates a Negative High Voltage (NHV) to apply to the word line during an erasing operation. | ¶41b | col. 3:51-54 |
| A positive voltage generating circuit for applying a positive voltage to a well...when the negative voltage reaches a predetermined voltage, wherein there is a timing gap between a start of the applying the negative voltage and a start of the applying the positive voltage. | The accused products include a circuit that generates a Positive High Voltage (PHV) applied to the well when the negative voltage has reached a pre-determined level, creating a timing gap. | ¶41c | col. 4:45-51 |
No probative visual evidence provided in complaint.
- Identified Points of Contention:
- Technical Questions: The central technical question will be whether the accused devices' erasing operations are controlled by the specific sequence claimed. The complaint alleges the positive voltage is applied "when the negative voltage has reached a pre-determined level," suggesting a causal link. Evidence will be needed to establish that the accused circuits operate based on this condition rather than, for example, on independent timers that create an incidental delay.
- Scope Questions: The term "timing gap" will likely be a focus of claim construction. The claim requires a gap "between a start of the applying the negative voltage and a start of the applying the positive voltage." A question for the court may be whether this requires the positive voltage application to begin after the negative voltage application has started but before it has ended, as depicted in the patent's figures (’968 Patent, Figs. 2, 6), or if it can cover other temporal arrangements.
V. Key Claim Terms for Construction
Patent: ’300 Patent
- The Term: "spillover electrons"
- Context and Importance: This term defines the specific problem the invention purports to solve. The infringement case for the ’300 patent may depend on whether the accused devices generate a phenomenon that falls within the scope of this term. Practitioners may focus on this term because its definition could be limited to the specific context provided in the patent's embodiments.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent's abstract and summary of the invention refer to "spillover electrons" generally, without explicit limitation to a specific memory cell architecture, which may support a broader application (’300 Patent, Abstract; col. 2:8-12).
- Evidence for a Narrower Interpretation: The detailed description and Figure 6A specifically depict "spillover electrons" as charge that has spread from a programmed region (e.g., the "right bit") to an adjacent region (near the "left bit") within a two-bit cell, potentially limiting the term to this specific intra-cell interference phenomenon (’300 Patent, Fig. 6A, col. 5:4-16).
Patent: ’968 Patent
- The Term: "when the negative voltage reaches a predetermined voltage"
- Context and Importance: This phrase establishes the conditional and temporal relationship between the two voltage application steps, which is a core feature of the claim. The infringement analysis will turn on whether the accused devices' positive voltage circuits are triggered by this specific event.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party could argue "when" is used in a less strict sense, meaning "at or after the time that" the voltage is reached, without requiring a direct triggering mechanism.
- Evidence for a Narrower Interpretation: The patent’s flow chart in Figure 5 shows a specific decision step ("IS, NEGATIVE VOLTAGE PREDETERMINED VOLTAGE?") that directly leads to the step of applying the positive voltage, suggesting a direct, causal trigger mechanism (’968 Patent, Fig. 5). This supports an interpretation where the positive voltage application is conditionally dependent on the negative voltage reaching the specified level.
VI. Other Allegations
- Indirect Infringement: The complaint alleges both induced and contributory infringement for all asserted patents. Inducement is based on allegations that Defendants provide user manuals and product documentation and recommend modes of operation that instruct customers on using the accused products in an infringing manner (Compl. ¶¶32, 43, 55, 67). Contributory infringement is based on allegations that the accused products constitute a material part of the inventions and are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶¶33, 44, 56, 68).
- Willful Infringement: Willfulness is alleged for all four patents based on pre-suit knowledge. The complaint alleges that Defendant Renesas was notified of the ’968 Patent as early as October 2017, the ’300 Patent as early as December 2017, and the ’133 and ’688 Patents as early as March 2022 (Compl. ¶¶25, 36, 47, 59, 71). The complaint alleges that despite this knowledge, Defendants continued their infringing conduct (Compl. ¶25.f).
VII. Analyst’s Conclusion: Key Questions for the Case
- A central issue will be one of functional operation: can Plaintiff produce evidence that the accused semiconductor devices perform their memory erase and system reset functions using the specific physical phenomena and conditional timing sequences required by the claims? This will involve detailed analysis of the accused products' circuit-level behavior, particularly regarding the existence of "spillover electrons" (’300 Patent) and the precise triggering mechanism for voltage application during an erase cycle (’968 Patent).
- A second key issue will be one of architectural correspondence: do the functional blocks within the accused Renesas microcontrollers, such as their reset circuits and mixed-signal components, map onto the specific multi-part structures defined in the claims of the ’133 and ’688 patents? This may turn on the construction of terms defining the claimed "first, second, and third reset functions" (’133 Patent) and the specific arrangement of analog blocks, digital blocks, and interconnects (’688 Patent).