DCT

2:24-cv-00239

Eireog Innovations Ltd v. Lenovo Group Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:24-cv-00239, E.D. Tex., 06/04/2024
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation, making venue appropriate in any U.S. judicial district. The complaint further alleges that Lenovo transacts business within the district through direct online sales and a network of authorized retail partners.
  • Core Dispute: Plaintiff alleges that Defendant’s servers, workstations, laptops, and desktops, which incorporate certain Intel and AMD processors, infringe five U.S. patents concerning processor architecture, including interrupt management, cache coherency, and power management.
  • Technical Context: The patents-in-suit relate to foundational technologies for managing performance, power, and data handling in modern multi-core and virtualized computing environments.
  • Key Procedural History: This amended complaint was filed following an original complaint filed on April 11, 2024. The filing of the original complaint is cited by the Plaintiff to establish the date of Defendant's alleged knowledge of the patents for the purposes of indirect and willful infringement claims.

Case Timeline

Date Event
2009-05-07 ’399 Patent Priority Date
2010-09-21 ’777 Patent Priority Date
2010-11-25 ’805 Patent Priority Date
2012-02-14 ’399 Patent Issue Date
2012-08-09 ’626 and ’870 Patents Priority Date
2013-08-06 ’777 Patent Issue Date
2016-05-10 ’805 Patent Issue Date
2016-09-06 ’626 Patent Issue Date
2016-09-13 ’870 Patent Issue Date
2024-04-11 Original Complaint Filing Date (alleged knowledge date)
2024-06-04 Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - “Processor interrupt interface with interrupt partitioning and virtualization enhancements”

Issued September 6, 2016

The Invention Explained

  • Problem Addressed: The patent describes inefficiencies in data processing systems with multiple processors or virtualized environments, where interrupts can be delayed by contention for access to a central interrupt controller and by the software complexity required to route interrupts to the correct partition (e.g., a guest operating system) (’626 Patent, col. 1:11-40).
  • The Patented Solution: The invention proposes a processor-based interrupt management system that uses special purpose registers located directly on the processor core. These registers store information like partition identifiers and priority levels, allowing the processor core to evaluate and manage interrupts locally without requiring memory-mapped operations to an external controller for every decision, thereby reducing latency (’626 Patent, Abstract; col. 2:15-46). Figure 2 of the patent illustrates these registers as part of the virtual core architecture (’626 Patent, Fig. 2).
  • Technical Importance: This architectural approach aims to reduce software overhead and improve interrupt response time, which is critical for performance in complex, virtualized computing systems like modern servers (’626 Patent, col. 2:47-67).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (’626 Patent, Compl. ¶16).
  • Claim 1 describes a method of managing interrupts at a processor, including:
    • Receiving an interrupt package from an interrupt controller.
    • The package includes an interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier.
    • Processing the package against one or more partitions by comparing the priority value and partition identifier against stored values in special purpose registers on the processor.
    • Determining on a partition basis whether the interrupt request is blocked or forwarded to a targeted thread.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 9,442,870 - “Interrupt priority management using partition-based priority blocking processor registers”

Issued September 13, 2016

The Invention Explained

  • Problem Addressed: The patent identifies challenges in managing interrupt priority in systems with multiple logical partitions, where traditional blocking mechanisms operate on a per-processor-core basis, which is too coarse and can lead to unnecessary blocking of interrupts for different partitions running on the same core (’870 Patent, col. 1:11-24).
  • The Patented Solution: The invention discloses using dedicated priority blocking registers on the processor core (e.g., an "INTLEVEL" register for a hypervisor and a "GINTLEVEL" register for a guest operating system). These registers allow different software partitions to independently set their own interrupt priority thresholds, enabling more granular and efficient interrupt management (’870 Patent, Abstract; col. 2:25-39). The relationship between these registers and a processor core is depicted in Figure 2 of the patent (’870 Patent, Fig. 2).
  • Technical Importance: This method provides finer-grained, partition-aware control over interrupt processing, which can improve system responsiveness and efficiency in virtualized environments (’870 Patent, col. 2:40-45).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (’870 Patent, Compl. ¶26).
  • Claim 1 describes a method of managing interrupts at a processor, including:
    • Receiving an interrupt package with a first priority value and a first partition identifier.
    • Processing the package by comparing the values against stored priority levels and partition identifiers in special purpose registers.
    • Determining on a partition basis if the interrupt is blocked or forwarded.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,504,777 - “Data processor for processing decorated instructions with cache bypass”

Issued August 6, 2013

  • Technology Synopsis: The patent addresses the problem of maintaining data consistency when an external "intelligent memory" can modify data atomically, potentially leaving the processor's cache with stale information (’777 Patent, col. 1:12-40). The invention describes "decorated instructions" that signal to the processor to bypass its cache. If an access for a decorated instruction results in a cache hit, the corresponding cache entry is invalidated to force a retrieval of the up-to-date value from the target memory, thereby ensuring cache coherency (’777 Patent, Abstract; col. 2:48-67).
  • Asserted Claims: Independent claim 16 (Compl. ¶36).
  • Accused Features: The complaint alleges that CPUs in the Accused Products, including Intel Skylake-based and AMD EPYC processors, perform cache bypass operations that practice the claimed invention (Compl. ¶35).

U.S. Patent No. 8,117,399 - “Processing of coherent and incoherent accesses at a uniform cache”

Issued February 14, 2012

  • Technology Synopsis: This patent addresses performance issues in systems with unified caches that store both instructions and data. Treating all cached information as "coherent" generates excessive system traffic from "snooping" to ensure data consistency, which is often unnecessary for instruction fetches that are rarely modified (’399 Patent, col. 1:11-26). The invention proposes marking cache lines as "coherent" or "incoherent." A coherent read (e.g., a data load) that targets a line marked "incoherent" is treated as a cache miss, forcing a coherency check. This reduces snoop traffic for incoherent accesses like instruction fetches (’399 Patent, Abstract).
  • Asserted Claims: Independent claim 14 (Compl. ¶46).
  • Accused Features: The complaint alleges that CPUs in the Accused Products utilize unified caches that manage coherent and incoherent accesses in an infringing manner (Compl. ¶45).

U.S. Patent No. 9,335,805 - “Method and apparatus for managing power in a multi-core processor”

Issued May 10, 2016

  • Technology Synopsis: The patent addresses the complexity of power management in multi-core processors, where increasing the number of active cores does not always improve power efficiency due to factors like static power leakage and how well a task can be parallelized (’805 Patent, col. 1:10-22). The invention describes a method for managing power by determining usage characteristics (such as a workload's "split-ability" and the processor's leakage current) and adapting the frequency, voltage, and/or number of enabled cores accordingly to optimize power consumption (’805 Patent, Abstract).
  • Asserted Claims: Independent claim 6 (Compl. ¶56).
  • Accused Features: The complaint alleges that products incorporating Intel Core CPUs (12th Generation "Alder Lake" and newer) implement these sophisticated power management techniques (Compl. ¶55).

III. The Accused Instrumentality

Product Identification

The complaint identifies a broad range of Lenovo products, categorized as servers (ThinkSystem), workstations (ThinkStation), desktops (ThinkCentre), and laptops (ThinkPad, Legion, IdeaPad, Yoga) that incorporate specific families of Intel and AMD processors (CPUs) (Compl. ¶15, ¶25, ¶35, ¶45, ¶55). The infringement allegations are tied to the functionality of these underlying CPUs, including Intel Haswell, Skylake, and Alder Lake (12th Gen) architectures and newer, as well as AMD Zen-based EPYC CPUs (Compl. ¶15, ¶35).

Functionality and Market Context

The complaint alleges that the identified Intel and AMD CPUs, when incorporated into and used within Lenovo's products, perform the patented technologies for interrupt management, cache coherency, and power management (Compl. ¶¶16, 26, 36, 46, 56). The complaint references Lenovo's own marketing materials and technical documentation to allege that Lenovo advertises and instructs customers on how to use the benefits of these accused functionalities (Compl. ¶¶18, 28, 38, 48, 58). For example, the complaint provides a link to a user guide for a representative accused laptop, which contains instructions and diagrams for configuring and using the product. (Compl. Ex. 23).

IV. Analysis of Infringement Allegations

’626 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of managing interrupts at a processor, comprising: receiving at the processor an interrupt package provided by an interrupt controller, where the interrupt package comprises a first interrupt request, an interrupt identifier ... a partition identifier ... a priority value ... and a thread identifier... The Accused Products, containing CPUs with virtualization technologies (e.g., Intel VT-d), are alleged to receive interrupt packages that include identifiers for partitions (e.g., virtual machines) and threads. ¶15, ¶16, ¶18 col. 5:6-15
processing the interrupt package against one or more partitions running on the processor by comparing the priority value and partition identifier against at least a stored priority level and stored partition identifier retrieved from special purpose registers at the processor The CPUs in the Accused Products allegedly contain and use special purpose registers (such as those for managing virtualization) to compare the received interrupt's partition and priority information against stored values to manage interrupt delivery. ¶15, ¶16, ¶18 col. 5:44-67
to determine on a partition basis if the first interrupt request is blocked or forwarded to a targeted thread identified by the thread identifier. Based on the comparison, the CPUs in the Accused Products allegedly determine whether to block an interrupt or forward it to the specific targeted thread (virtual core) corresponding to a software partition, such as a guest OS or hypervisor. ¶15, ¶16, ¶18 col. 6:1-10
  • Identified Points of Contention:
    • Scope Questions: A central question will be whether the specific architectural implementations in the accused Intel and AMD CPUs meet the definition of "special purpose registers" as claimed. Defendant may argue that their processors use general-purpose architectural features that are configured by software to achieve a similar result, rather than the specific hardware structure claimed in the patent.
    • Technical Questions: The complaint alleges that the processors receive an "interrupt package" containing all the listed identifiers. A technical question is what evidence demonstrates that these distinct pieces of information are bundled and processed as a single "package" in the manner required by the claim, as opposed to being handled through separate, unbundled mechanisms.

’870 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of managing interrupts at a processor, comprising: processing an interrupt package for a first physical interrupt request ... the interrupt package comprises a first priority value and a first partition identifier... The Accused Products, through their processors, are alleged to process interrupts that are associated with a specific priority level and are targeted to a specific software partition (e.g., a virtual machine). ¶25, ¶26, ¶28 col. 7:13-17
processing the interrupt package ... by comparing the first priority value and first partition identifier against at least a stored priority level retrieved from one or more special purpose priority blocking registers at the processor to determine ... if the first physical interrupt request is blocked or forwarded... The CPUs in the Accused Products are alleged to contain special purpose registers (e.g., INTLEVEL, GINTLEVEL) that store priority thresholds for different partitions. These are used to determine whether to block or forward an incoming interrupt based on its partition and priority. ¶25, ¶26, ¶28 col. 8:1-12
  • Identified Points of Contention:
    • Scope Questions: Does the term "special purpose priority blocking register" read on the interrupt control mechanisms in the accused CPUs? The dispute may focus on whether the accused registers are truly "special purpose" for partition-based blocking, as described in the patent, or are part of a more general interrupt control framework that lacks the specific claimed structure.
    • Technical Questions: What evidence does the complaint provide that the accused processors perform the comparison and determination "on a partition basis" using the specific register-based logic claimed, rather than through a more centralized or software-driven method that may produce a similar outcome but operate differently at a technical level? The complaint supports this by referencing product user guides, such as one for a ThinkAgile system. (Compl. Ex. 9).

V. Key Claim Terms for Construction

  • For the ’626 and ’870 Patents:
    • The Term: "special purpose register"
    • Context and Importance: This term appears in the independent claims of both lead patents and is central to the patented inventions, which move interrupt logic from a general controller to dedicated hardware on the processor core. The infringement analysis will depend heavily on whether the registers within the accused Intel and AMD CPUs, which manage interrupts and virtualization, are construed as "special purpose" in the manner claimed.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the function of these registers as storing interrupt context information to provide management capability without requiring stack ordering by software (’626 Patent, col. 2:56-62). This functional description could support a broader definition covering any register that achieves this purpose.
      • Evidence for a Narrower Interpretation: The patents explicitly depict and name specific registers like "LPIDR", "EPR", "INTLEVEL", and "GINTLEVEL" in the figures and detailed description (’626 Patent, Fig. 2; ’870 Patent, col. 2:25-39). A defendant may argue that the term should be limited to registers with the specific structures and interconnections shown in these embodiments.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement against Lenovo. The basis for inducement is the allegation that Lenovo provides customers with its products along with user manuals, setup guides, marketing materials, and other instructions that actively encourage and instruct end-users to use the accused products in their normal, infringing manner (Compl. ¶¶18, 28, 38, 48, 58).
  • Willful Infringement: The complaint alleges that Lenovo's infringement has been and continues to be willful. This allegation is based on Lenovo's alleged continued infringement after gaining knowledge of the Asserted Patents and its infringement, at least as of the filing date of the original complaint on April 11, 2024 (Compl. ¶¶18, 28, 38, 48, 58). The complaint also alleges contributory infringement, stating that the accused features are a material part of the inventions and are not staple articles of commerce (Compl. ¶¶19, 29, 39, 49, 59).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of claim construction and scope: can the term "special purpose register," as described in the patents in the context of a novel on-core interrupt architecture, be construed to read on the established, multi-functional virtualization and interrupt control registers implemented in commercial CPUs by third-party manufacturers like Intel and AMD?
  • A key evidentiary question will be one of technical proof: beyond pointing to high-level product features, what specific, non-public technical evidence can Plaintiff discover and present to demonstrate that the internal operations of the accused processors map to every limitation of the asserted claims, particularly for the patented methods of processing cache accesses and managing power?
  • A central question for damages will be apportionment: given that the patents-in-suit cover specific features within highly complex microprocessors—which are themselves components within larger computer systems—the case will raise the question of how to reliably apportion the value of the allegedly infringing functionality from the immense value of the non-infringing aspects of the CPUs and the final Lenovo products.