Eireog Innovations Ltd v. Hewlett Packard Enterprises Co

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Eireog Innovations Ltd. (Ireland)
  • Defendant: Hewlett Packard Enterprise Company (Delaware)
  • Plaintiff’s Counsel: BC Law Group, P.C.
• Case Identification: 2:24-cv-00279, E.D. Tex., 04/25/2024
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant is registered to do business in Texas, has transacted business in the District, and maintains regular and established places of business within the District.
• Core Dispute: Plaintiff alleges that Defendant’s server, supercomputing, and storage products, which incorporate certain Intel and AMD processors, infringe four patents related to processor interrupt management, instruction processing, and cache coherency.
• Technical Context: The technology concerns fundamental methods in computer architecture for managing how processors handle external requests (interrupts) and access data (cache management) to enhance performance and efficiency in complex, multi-core, and virtualized systems.
• Key Procedural History: The complaint does not allege any pre-suit litigation, licensing history, or administrative proceedings concerning the Asserted Patents. Plaintiff served infringement claim charts concurrently with the filing of the complaint.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - "Processor interrupt interface with interrupt partitioning and virtualization enhancements"

• Patent Identification: U.S. Patent No. 9,436,626, "Processor interrupt interface with interrupt partitioning and virtualization enhancements," issued September 6, 2016. (Compl. ¶8).

The Invention Explained

• Problem Addressed: In data processing systems with multiple processors or virtualized partitions, interrupts can be delayed when multiple processors vie for access to a central interrupt controller, which adds software complexity and degrades system performance. (’626 Patent, col. 1:13-33).
• The Patented Solution: The patent describes moving interrupt management logic, particularly priority blocking, from a central controller directly into the processor core. This is accomplished using "special purpose registers" on the processor that store partition-specific blocking rules. An incoming interrupt includes a "partition identifier," allowing the processor core to evaluate the interrupt against the correct partition's rules without needing to involve a hypervisor for every request. (’626 Patent, col. 2:15-46; Fig. 2).
• Technical Importance: This architecture aims to reduce interrupt latency and simplify controller design in complex virtualized systems by allowing different software partitions to manage their own interrupt priorities independently and directly on the processor hardware. (’626 Patent, col. 2:23-34).

Key Claims at a Glance

• The complaint asserts at least independent claim 1. (Compl. ¶10).
• The essential elements of independent claim 1 include:
  • Receiving, at a processor, an interrupt package that includes a first interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier.
  • Processing the interrupt package against one or more partitions by comparing the priority value and partition identifier against a stored priority level and stored partition identifier retrieved from special purpose registers at the processor.
  • Determining on a partition basis whether the first interrupt request is blocked or forwarded to a targeted thread identified by the thread identifier.
• The complaint does not explicitly reserve the right to assert other claims, though this is common practice.

U.S. Patent No. 9,442,870 - "Interrupt priority management using partition-based priority blocking processor registers"

• Patent Identification: U.S. Patent No. 9,442,870, "Interrupt priority management using partition-based priority blocking processor registers," issued September 13, 2016. (Compl. ¶18).

The Invention Explained

• Problem Addressed: The patent identifies performance issues in systems with multiple partitions, where interrupt priority blocking is handled by a central controller. This approach can be slow and requires complex software management, especially when routing interrupts to the correct partition. (’870 Patent, col. 1:15-30).
• The Patented Solution: The invention discloses a method where interrupt priority blocking is controlled by special purpose registers located within the processor core itself. An interrupt request is presented with a partition identifier, which the processor core uses to select the appropriate set of on-core registers to determine if the interrupt should be blocked or forwarded, all based on rules specific to that partition. (’870 Patent, col. 2:1-24; Fig. 2).
• Technical Importance: By decentralizing partition-based priority blocking to the processor core, the invention seeks to reduce software overhead and access delays associated with a central interrupt controller. (’870 Patent, col. 2:5-10).

Key Claims at a Glance

• The complaint asserts at least independent claim 1. (Compl. ¶20).
• The essential elements of independent claim 1 include:
  • Receiving at the processor an interrupt package for a physical interrupt request, the package comprising a first priority value and a first partition identifier.
  • Processing the package by comparing the priority value and partition identifier against a stored priority level and stored partition identifier retrieved from special purpose registers at the processor.
  • Determining on a partition basis if the physical interrupt request is blocked or forwarded.
• The complaint does not explicitly reserve the right to assert other claims.

U.S. Patent No. 8,504,777 - "Data processor for processing decorated instructions with cache bypass"

• Patent Identification: U.S. Patent No. 8,504,777, "Data processor for processing decorated instructions with cache bypass," issued August 6, 2013. (Compl. ¶28).
• Technology Synopsis: The patent addresses a data coherency problem that arises when certain specialized instructions, termed "decorated instructions," modify data directly in a target memory, rendering any cached version of that data stale. The disclosed solution involves the processor identifying such instructions, bypassing the cache for the operation, and, if a cache hit occurs, invalidating the stale cache entry to maintain data integrity. (’777 Patent, Abstract; col. 2:48-65).
• Asserted Claims: The complaint asserts at least independent claim 16. (Compl. ¶30).
• Accused Features: The complaint accuses the "cache processing features" of HPE products containing Intel Skylake-based and newer CPUs, and AMD EPYC CPUs. (Compl. ¶¶ 29, 33).

U.S. Patent No. 8,117,399 - "Processing of coherent and incoherent accesses at a uniform cache"

• Patent Identification: U.S. Patent No. 8,117,399, "Processing of coherent and incoherent accesses at a uniform cache," issued February 14, 2012. (Compl. ¶38).
• Technology Synopsis: This patent describes a method for managing coherency in a unified cache storing both instructions and data. The solution involves marking each cacheline as either "coherent" or "incoherent." A coherent read access (e.g., a data load) that targets a line marked "incoherent" is treated as a cache miss, forcing a system-wide "snoop" to find the correct data, while an incoherent read access (e.g., an instruction fetch) can be a hit on either type. (’399 Patent, Abstract; col. 2:1-25). This technique reduces snoop traffic associated with instruction fetches, which typically do not require coherency.
• Asserted Claims: The complaint asserts at least independent claim 14. (Compl. ¶40).
• Accused Features: The complaint accuses the "accused cache processing features" of HPE products containing Intel Skylake-based and newer CPUs, and AMD EPYC CPUs. (Compl. ¶¶ 39, 43).

III. The Accused Instrumentality

• Product Identification: The complaint identifies a wide range of Defendant’s products as the "Accused Products," including various generations of HPE's ProLiant Servers, Apollo Servers, Alletra Storage, Cray Supercomputing systems, and SimpliVity platforms. (Compl. ¶¶ 9, 19, 29, 39).
• Functionality and Market Context: The infringement allegations are directed at the functionality of the central processing units (CPUs) incorporated into the Accused Products, specifically "Intel-based CPUs (Haswell-based architecture and newer)," "Intel-based CPUs (Skylake-based architecture and newer)," and "AMD Zen-based CPUs," including AMD EPYC processors. (Compl. ¶¶ 9, 29, 39). The complaint alleges that these CPUs contain the processor interrupt management and cache processing features claimed by the Asserted Patents. Plaintiff further alleges that HPE advertises the benefits of these Intel and AMD processors in its products, suggesting their commercial importance. (Compl. ¶¶ 12, 22, 32, 42).

IV. Analysis of Infringement Allegations

The complaint alleges that the Accused Products directly infringe the Asserted Patents by satisfying all claim limitations. (Compl. ¶¶ 10, 20, 30, 40). For each asserted patent, the complaint references claim chart exhibits (Exhibits 2-3, 10-11, 13-14, 16-17) that purportedly compare the exemplary independent claims to the Accused Products. (Compl. ¶¶ 10, 20, 30, 40). These exhibits were not provided with the complaint document, precluding a detailed, element-by-element analysis of the infringement allegations.

No probative visual evidence provided in complaint.

The narrative theory of infringement for the '626 and '870 patents appears to be that the accused Intel and AMD CPUs, when operating in the Accused Products, implement a partition-based interrupt management system. This system allegedly receives an "interrupt package" containing partition and priority information and uses on-core "special purpose registers" to apply partition-specific blocking rules, thereby mapping directly onto the structures and methods recited in the asserted claims.

• Identified Points of Contention:
  • Architectural Equivalence: A primary question will be whether the specific hardware registers, logic, and signaling protocols used in the accused Intel and AMD CPUs function in the same way as the claimed "special purpose registers" and "interrupt package". The dispute may focus on whether the commercial implementations are structurally and functionally equivalent to the claimed architecture or represent a distinct, non-infringing approach.
  • Functional Mapping: The analysis will likely raise the question of whether the accused processors, in operation, perform all steps of the asserted method claims. For example, for the '626 patent, a factual question will be whether the accused system processes an "interrupt package" that contains all five required components (request, interrupt ID, partition ID, priority value, and thread ID) as claimed.

V. Key Claim Terms for Construction

• The Term: "special purpose registers at the processor" ('626 Patent, claim 1; '870 Patent, claim 1)

  • Context and Importance: The location and function of these registers are central to the claimed invention, distinguishing it from systems where interrupt logic resides in a separate controller. The construction of this term will be critical to determining whether the architecture of the accused CPUs falls within the scope of the claims. Practitioners may focus on this term because its definition will dictate whether a wide range of modern CPU hardware infringes.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes these registers functionally as storing priority levels and partition identifiers to evaluate partition ownership and priority. (’626 Patent, col. 2:18-22). This functional description could support a construction that is not limited to the specific register names or configurations shown in the embodiments.
    • Evidence for a Narrower Interpretation: The figures and detailed description illustrate specific examples, such as a "guest priority blocking register" and a "VMM priority blocking register." (’626 Patent, Fig. 2; col. 5:10-20). A defendant could argue that the term should be limited to registers with this explicit purpose and structure, rather than any general-purpose register that might be configured by software to store similar information.

• The Term: "partition identifier" ('626 Patent, claim 1; '870 Patent, claim 1)

  • Context and Importance: Infringement hinges on demonstrating that the accused systems use an identifier to associate an interrupt with a specific partition for blocking purposes. How broadly or narrowly this term is defined will determine what type of data or signal satisfies this claim element.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent describes the identifier's purpose as allowing the system to "direct the interrupt to the recipient partition (e.g., hypervisor or guest)." (’626 Patent, col. 5:5-9). This could support a broad, functional definition covering any data that achieves this result.
    • Evidence for a Narrower Interpretation: The specification also refers to a specific "logical partition identifier (LPID)." (’626 Patent, col. 5:23-28). A party might argue this implies the term requires an explicit, designated field for the partition ID, not just any data from which a partition could be inferred.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all four patents. The stated basis for inducement is that HPE provides customers with "user manuals and online instruction materials" that allegedly instruct and encourage end users to configure and use the Accused Products in a manner that directly infringes the patents. (Compl. ¶¶ 12, 22, 32, 42).
• Willful Infringement: The complaint includes allegations of willful infringement. The basis for willfulness is alleged knowledge of the patents and infringement "at least as of the filing and service of this complaint," which was accompanied by infringement claim charts. (Compl. ¶¶ 12, 22, 32, 42). The complaint does not allege any pre-suit knowledge.

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this dispute will likely depend on the court's determination of the following central questions:

• A core issue will be one of architectural mapping: Do the complex interrupt and cache management mechanisms implemented in the accused high-performance Intel and AMD CPUs constitute the specific systems claimed in the Asserted Patents? The case will likely turn on whether the accused functionality of on-chip registers for interrupt blocking ('626 and '870 patents) and cache coherency for specialized instructions ('777 and '399 patents) is functionally and structurally equivalent to the patent claims, or represents a fundamentally different, non-infringing design.
• A key evidentiary question will be one of definitional scope: Can terms like "partition identifier" and "special purpose registers", which are rooted in the specific embodiments of the patents, be construed broadly enough to read on the multifaceted signaling protocols and configurable hardware of modern server processors? The outcome may depend on whether the evidence shows the accused systems use signals and hardware that meet these definitions as they would be understood by a person of ordinary skill in the art at the time of the inventions.