Eireog Innovations Ltd v. Acer Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Eireog Innovations Limited (Ireland)
  • Defendant: Acer Incorporated (Taiwan)
  • Plaintiff’s Counsel: BC LAW GROUP, Group
• Case Identification: 2:24-cv-00449, E.D. Tex., 08/13/2024
• Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation, making venue appropriate in any judicial district. The complaint further alleges that Acer transacts business and has committed acts of infringement in the district, and has not contested venue in prior actions in the same court.
• Core Dispute: Plaintiff alleges that Defendant’s laptops and desktops incorporating certain Intel and AMD CPUs infringe two patents related to managing processor interrupts in partitioned and virtualized environments.
• Technical Context: The technology concerns methods for efficiently handling and prioritizing interrupt requests in multi-core processors, a fundamental process for performance in modern computing systems, particularly in virtualized data centers and complex operating systems.
• Key Procedural History: The filing is an amended complaint, indicating a prior version was filed. The complaint alleges that Defendant was put on notice of the asserted patents and its infringement via claim charts served with the original complaint. To support jurisdiction and venue, the complaint also references prior litigation involving the defendant in the same district, Atlas Glob. Techs. LLC v. Acer Inc.

Case Timeline

Date	Event
2012-08-09	Priority Date for ’626 and ’870 Patents
2016-09-06	U.S. Patent No. 9,436,626 Issues
2016-09-13	U.S. Patent No. 9,442,870 Issues
2024-08-13	Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626

• Patent Identification: U.S. Patent No. 9,436,626, “Processor interrupt interface with interrupt partitioning and virtualization enhancements,” issued September 6, 2016. (Compl. ¶10).

The Invention Explained

• Problem Addressed: In computer systems with multiple processors or virtualized environments, managing interrupt requests can be slow and complex. Traditional interrupt controllers often create performance bottlenecks and add software overhead, especially when an interrupt is intended for a partition (e.g., a virtual machine) that is not currently active. (’626 Patent, col. 1:13-44).
• The Patented Solution: The invention moves key aspects of interrupt management from a separate controller onto the processor core itself. It proposes using "special purpose registers" located on the processor to store information about partitions and priority levels. When an interrupt arrives, its associated data (e.g., partition ID, priority) is compared against the values in these on-core registers to quickly determine if the interrupt should be blocked or passed to a specific software thread, bypassing the need for slower, memory-mapped operations or hypervisor intervention for every decision. (’626 Patent, Abstract; col. 2:18-47).
• Technical Importance: This design aims to reduce latency and software complexity in virtualized systems, which are foundational to modern cloud computing and enterprise servers. (’626 Patent, col. 2:23-34).

Key Claims at a Glance

• The complaint asserts independent claim 1 and notes infringement of "one or more claims." (Compl. ¶11-12).
• Independent Claim 1 of the ’626 Patent recites:
  • Receiving at the processor an interrupt package from an interrupt controller, where the package includes a first interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier.
  • Processing the interrupt package against partitions running on the processor by comparing the priority value and partition identifier against a stored priority level and stored partition identifier retrieved from special purpose registers at the processor.
  • Determining on a partition basis whether the interrupt request is blocked or forwarded to a targeted thread.

U.S. Patent No. 9,442,870

• Patent Identification: U.S. Patent No. 9,442,870, “Interrupt priority management using partition-based priority blocking processor registers,” issued September 13, 2016. (Compl. ¶20).

The Invention Explained

• Problem Addressed: The patent identifies the same core problem as its related ’626 Patent: conventional interrupt controllers create performance issues and require complex software management in partitioned systems where multiple operating systems or virtual machines run concurrently. (’870 Patent, col. 1:12-32).
• The Patented Solution: The invention describes a processor core architecture with special purpose registers that control interrupt blocking on a partition-by-partition basis. An incoming interrupt's partition identifier (LPID) is used to select the appropriate on-processor register, and its priority level is then compared to a value in that register to decide whether to block or forward the interrupt to the target virtual processor. This moves the priority blocking logic directly onto the processor core. (’870 Patent, Abstract; col. 2:1-24).
• Technical Importance: By enabling more direct, hardware-based control of interrupt routing in virtualized environments, this method seeks to improve system efficiency and responsiveness. (’870 Patent, col. 2:5-14).

Key Claims at a Glance

• The complaint asserts independent claim 1 and alleges infringement of "one or more claims." (Compl. ¶21-22).
• Independent Claim 1 of the ’870 Patent recites:
  • Receiving at the processor an interrupt package for a physical interrupt request, which includes a priority value and a partition identifier.
  • Processing the package against partitions running on targeted virtual processors by comparing the priority value and partition identifier against a stored priority level and stored partition identifier from special purpose registers.
  • Determining on a partition basis if the interrupt is blocked or forwarded to a targeted virtual processor.

III. The Accused Instrumentality

• Product Identification: The complaint identifies the Accused Products as a broad range of Acer-branded laptops and desktops that incorporate either Intel-based CPUs (Haswell architecture and newer) or AMD Zen-based CPUs. (Compl. ¶11, 21). Specific product lines mentioned include Aspire, Chromebox, Nitro, Predator, Veriton, TravelMate, and Swift. (Compl. ¶11, 21).
• Functionality and Market Context: The infringement allegations target the core "processor interrupt management features" of the CPUs within the Accused Products. (Compl. ¶15, 25). The complaint alleges these products are commercially significant and widely distributed in the United States through Acer's website and national retailers, including Best Buy, Costco, Office Depot, and Target located within the Eastern District of Texas. (Compl. ¶4). The accused functionality is fundamental to how these computers manage tasks and respond to hardware and software events.

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits (Exhibits 3, 4, 6, and 7) that purportedly detail the infringement of the Asserted Patents. (Compl. ¶12, 22). In the absence of these exhibits, the infringement theory is derived from the narrative allegations.

The complaint’s narrative theory is that the accused Intel and AMD CPUs in Acer’s products perform the patented methods. It alleges these CPUs receive interrupt signals that contain, or are associated with, information corresponding to the claimed "interrupt package," including identifiers for partitions (e.g., virtual machines or protected contexts), threads, and priority levels. (Compl. ¶11, 21). The complaint further contends that these CPUs use on-chip "special purpose registers" to implement a "partition-based" blocking mechanism, whereby the incoming interrupt's information is compared against stored values to determine if the interrupt should be blocked or forwarded to a specific processor core or thread. (Compl. ¶12, 15, 22, 25). This alleged operation is presented as mapping directly onto the steps of the asserted independent claims of the ’626 and ’870 patents.

No probative visual evidence provided in complaint.

• Identified Points of Contention:
  • Scope Questions: A central dispute may concern the definition of "partition." The patents describe partitions primarily in the context of hypervisors and guest operating systems. (’626 Patent, col. 4:38-46). A question for the court will be whether the architectural features of the accused Intel and AMD CPUs (e.g., security enclaves, different operating modes) meet the claimed definition of a "partition."
  • Technical Questions: The complaint alleges the use of "special purpose registers" but does not identify specific registers in the accused CPUs. (Compl. ¶12, 22). A key technical question will be whether the plaintiff can provide evidence that the accused CPUs contain registers that function as claimed, as opposed to using general-purpose registers or a different logic structure to manage interrupts. Further, it raises the question of whether the accused functionality operates "on a partition basis" as required by the claims, or on a simpler priority-only basis.

V. Key Claim Terms for Construction

• The Term: "interrupt package" (from Claim 1 of the ’626 Patent)

• Context and Importance: This term defines the set of information required to trigger the patented method. The infringement analysis will depend on whether the interrupt signals in the accused CPUs contain all components of the claimed "package" (e.g., interrupt ID, partition ID, thread ID, priority).

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The specification suggests the "package" is context information "conveyed with the interrupt request," which could support a more functional interpretation where the data does not need to be in a single, formally defined structure. (’626 Patent, col. 7:42-50).
  • Evidence for a Narrower Interpretation: The patent’s Figure 3 depicts discrete "communication conductors" for each piece of information (interrupt request 131, identifier 132, LPID 133, etc.). This may support a narrower construction requiring distinct, identifiable data elements corresponding to each part of the claimed "package." (’626 Patent, Fig. 3).

• The Term: "special purpose registers at the processor" (from Claim 1 of both patents)

• Context and Importance: This term is central to the invention's claimed novelty of moving interrupt logic onto the processor core. Practitioners may focus on this term because the case will likely hinge on whether registers within the accused commercial CPUs can be properly characterized as "special purpose" for partition-based interrupt blocking.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patents describe the function of these registers as storing partition IDs and priority levels for comparison during interrupt processing. (’626 Patent, col. 2:18-24; ’870 Patent, col. 2:1-10). A party could argue that any on-core register, regardless of its name, that is used to perform this specific function meets the definition.
  • Evidence for a Narrower Interpretation: The specifications provide specific examples of such registers, including "LPIDR," "INTLEVEL," and "GINTLEVEL." (’626 Patent, col. 5:1-11; ’870 Patent, col. 7:1-15). This could support an argument that the term is limited to registers that are structurally analogous and dedicated to this specific task, rather than being general-purpose registers temporarily used for it.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement, stating that Acer "actively encourage[s] and instruct[s] its customers and end users" to use the accused products in an infringing manner through materials like user manuals and online instructions. (Compl. ¶14, 24).
• Willful Infringement: The complaint alleges that Acer gained knowledge of the Asserted Patents and its infringement "At least as of the filing and service of the original complaint" and the claim charts provided with it. It alleges that Acer continues to infringe despite this knowledge, forming a basis for post-suit willfulness. (Compl. ¶14, 24). The prayer for relief requests a finding that the case is exceptional under 35 U.S.C. § 285. (Compl. p. 11, ¶e).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A central issue will be one of technical mapping: Can the plaintiff produce sufficient evidence to show that the complex, real-world operation of commercial Intel and AMD CPUs maps onto every element of the patent claims? This will require a granular analysis of whether the accused processors truly use "special purpose registers" to perform blocking "on a partition basis," as opposed to using different logic or criteria.
2. The outcome may also depend on a question of claim construction: Can the term "partition," which is rooted in the patent’s discussion of hypervisors and distinct operating systems, be construed to read on the architectural constructs (e.g., security modes, rings of privilege) used in the accused commercial CPUs?