InnoMemory LLC v. Shenzhen Longsys Electronics Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Shenzhen Longsys Electronics Co., Ltd (China)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00659, E.D. Tex., 08/13/2024
• Venue Allegations: Venue is alleged to be proper because the Defendant is a foreign corporation.
• Core Dispute: Plaintiff alleges that Defendant infringes a patent related to methods and architectures for reducing power consumption in memory devices during refresh operations.
• Technical Context: The technology concerns power-saving techniques for dynamic random-access memory (DRAM), which is critical for extending the battery life of portable electronic devices.
• Key Procedural History: The patent-in-suit is a continuation of an earlier application, U.S. Ser. No. 10/090,850, which issued as U.S. Patent No. 6,618,314. No other procedural events are mentioned in the complaint.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

• Issued: June 6, 2006

The Invention Explained

• Problem Addressed: In conventional dynamic random access memory (DRAM), memory cells must be periodically refreshed to retain data, a process that consumes significant power. This power consumption is particularly problematic in battery-powered devices in standby mode. The patent notes that a disadvantage of prior art partial-refresh techniques is that "the periphery array circuits of all four quadrants are activated when less than the full array... requires refreshing" ('960 Patent, col. 2:25-30).
• The Patented Solution: The invention proposes an architecture where a memory array is divided into multiple sections, each with its own "periphery array circuits" (e.g., sense amplifiers, wordline drivers). The invention allows for the selective control of these circuits, so that only the circuits corresponding to the memory sections being refreshed are activated, while the circuits for other sections remain disabled and do not draw power ('960 Patent, col. 3:25-33; Fig. 3). This enables a more granular and efficient partial-array refresh, thereby reducing overall standby power consumption.
• Technical Importance: This approach allows for lower standby power consumption in memory devices, which can directly affect the standby time for battery-powered mobile devices like portable telephones ('960 Patent, col. 1:30-34, col. 1:40-42).

Key Claims at a Glance

• The complaint does not identify specific asserted claims in its body, instead referring to "Exemplary '960 Patent Claims" in an attached exhibit not provided with the filing (Compl. ¶11, 13). Independent claims 1 and 10 are representative of the patent's scope.
• Independent Claim 1 (Method):
  • A method for reducing power consumption during background operations in a memory array with a plurality of sections.
  • Controlling the background operations in each section in response to one or more control signals.
  • The control signals are generated in response to a "programmable address signal."
  • The background operations can be enabled "simultaneously in two or more of said plurality of sections independently of any other section."
  • Presenting the control signals and decoded address signals to one or more "periphery array circuits" of the sections.
• Independent Claim 10 (Apparatus):
  • An apparatus comprising a memory array with a plurality of sections, each having memory cells and "periphery array circuitry."
  • A control circuit configured to present control and address signals to the periphery array circuitry.
  • The control signals are generated in response to a "programmable address signal."
  • A background operation in each section is controlled by the control signals and "can be enabled simultaneously in two or more of said plurality of sections independently of any other section."
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

• The complaint does not identify any accused products, methods, or services by name (Compl. ¶¶11-14).

Functionality and Market Context

• The complaint states that infringement allegations concerning "Exemplary Defendant Products" are detailed in claim charts included as Exhibit 2 (Compl. ¶13). As this exhibit was not provided with the complaint, the functionality and market context of the accused instrumentalities cannot be analyzed.

IV. Analysis of Infringement Allegations

The complaint does not contain a narrative infringement theory or any specific factual allegations mapping claim elements to accused product features. Instead, it "incorporates by reference" the allegations from "the claim charts of Exhibit 2," which was not provided with the complaint (Compl. ¶14). Therefore, a detailed analysis of the infringement allegations is not possible.

No probative visual evidence provided in complaint.

V. Key Claim Terms for Construction

"periphery array circuits"

• Context and Importance: This term is central to both the method and apparatus claims and defines the specific circuitry that is selectively controlled to save power. The infringement analysis will depend on whether the accused products contain structures that meet this definition and are controlled in the manner claimed.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes these circuits functionally as "support circuits for sections being refreshed" versus those not being refreshed ('960 Patent, col. 2:51-53). A party might argue this supports a functional definition covering any support circuitry that can be selectively powered down.
  • Evidence for a Narrower Interpretation: Dependent claim 5 explicitly lists examples of such circuits, stating they "comprise one or more circuits from the group consisting of sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" ('960 Patent, col. 11:59-65). A party may argue this list limits the scope of the term to these specific types of circuits or equivalents thereof. Figure 5 also depicts these specific circuit types as components of the periphery array circuit 152 (col. 6:50-57).

"background operations"

• Context and Importance: This term defines the type of memory functions to which the power-saving method applies. Its scope will determine whether the accused products' power management features for operations like self-refresh fall within the claims.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification states the invention can be "implemented to control other background memory access operations and/or housekeeping operations," suggesting a scope beyond just data refresh ('960 Patent, col. 8:20-22).
  • Evidence for a Narrower Interpretation: The claims and specification repeatedly emphasize "refresh operation" as the primary example ('960 Patent, Title; Abstract; Claim 2). A party could argue the term's scope should be construed in light of this primary focus, potentially excluding other types of low-power operations not analogous to a refresh. Claim 4 explicitly states the background operations "comprise parity checking" ('960 Patent, col. 11:59-60), which could be used to argue the term is limited to the specified examples of refresh and parity checking.

"enabled simultaneously in two or more of said plurality of sections independently of any other section"

• Context and Importance: Practitioners may focus on this term because it recites a specific and complex capability: independent and simultaneous control over multiple, but not necessarily all, memory sections. The infringement analysis will hinge on whether the accused devices' memory controllers possess this specific architectural feature.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification provides an example of refreshing "one-half of the memory array," which requires asserting signals for two of four sections simultaneously ('960 Patent, col. 8:12-16). This could support a reading that covers any form of partial-array operation.
  • Evidence for a Narrower Interpretation: The phrase "independently of any other section" may be argued to require a high degree of architectural separation and control that is distinct from conventional block-based or quadrant-based refresh schemes. The control mechanism is tied to a "programmable address signal" stored in a register, which dictates which sections are active ('960 Patent, col. 12:59-65; col. 4:55-65). This may suggest a narrower scope limited to systems using a similar programmable register-based control scheme.

VI. Other Allegations

• Indirect Infringement: The complaint does not contain any factual allegations to support a claim for indirect infringement (Compl. ¶¶1-16).
• Willful Infringement: The complaint does not allege pre- or post-suit knowledge or any other specific facts that would support a claim for willful infringement. The prayer for relief requests that the case be declared exceptional, but provides no factual basis for this request in the body of the complaint (Compl. ¶E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

As the complaint lacks specific factual allegations, the initial phase of the case will likely focus on discovery to resolve fundamental preliminary questions before the substantive dispute can take shape.

1. A threshold evidentiary question will be the identification of the accused products and their specific memory control architectures. Without this information, which the complaint incorporates by reference from an unprovided exhibit, no meaningful infringement analysis is possible.

2. A central issue will be one of claim scope: whether the term "periphery array circuits" is limited to the specific examples disclosed in the patent (e.g., sense amplifiers, wordline drivers), or if it can be construed more broadly to cover other types of support circuitry found in modern memory controllers.

3. The case will likely turn on a question of technical architecture: do the accused products, once identified, actually feature a control system that allows background operations in multiple memory sections to be "enabled simultaneously... independently of any other section," as required by the claims, or do they use a more conventional, less granular power management scheme?