InnoMemory LLC v. Advantech Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Advantech Co., Ltd. (Taiwan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00664, E.D. Tex., 08/13/2024
• Venue Allegations: Venue is alleged to be proper because the Defendant is a foreign corporation and has purportedly committed acts of patent infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant’s unspecified products infringe a patent related to methods for reducing power consumption in memory devices during refresh operations.
• Technical Context: The technology addresses power management in dynamic random-access memory (DRAM), a critical consideration for battery-powered electronic devices where standby power consumption affects operational life.
• Key Procedural History: The patent-in-suit is a continuation of a prior U.S. patent application, which may be relevant for determining the effective filing date and analyzing the prosecution history. The complaint does not mention any other prior litigation, licensing, or post-grant proceedings.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

• Patent Identification: U.S. Patent No. 7,057,960, issued June 6, 2006.

The Invention Explained

• Problem Addressed: The patent describes a problem in conventional dynamic semiconductor memories (DRAMs) where, during low-power standby modes, the entire memory array is refreshed even if only a portion contains data that needs to be retained ('960 Patent, col. 1:35-48). This is inefficient, as activating the support circuitry for all memory sections consumes unnecessary power, which is particularly disadvantageous for battery-powered devices ('960 Patent, col. 1:28-35). A specific disadvantage identified is that conventional systems activate the periphery array circuits for all memory quadrants even when refreshing less than the full array ('960 Patent, col. 2:25-29).
• The Patented Solution: The invention discloses a method and architecture for reducing power consumption by selectively refreshing only designated sections of a memory array ('960 Patent, Abstract). The core concept is to provide independent control over the "periphery array circuits" (e.g., wordline drivers, sense amplifiers) for each memory section ('960 Patent, col. 2:37-44; Fig. 2). By using dedicated control signals (e.g., REF0-REFn) to enable only the circuitry for sections being refreshed, the support circuits for all other sections can be left inactive, thereby saving power ('960 Patent, col. 3:47-54).
• Technical Importance: This selective refresh capability was significant for the growing market of mobile and portable electronics, where minimizing standby current could directly extend battery life ('960 Patent, col. 1:31-35).

Key Claims at a Glance

• The complaint alleges infringement of "one or more claims" but does not specify them, instead referring to "Exemplary '960 Patent Claims" in an attached exhibit not provided with the complaint (Compl. ¶¶11, 13). Independent Claim 1 is representative of the method claims.
• Independent Claim 1 (Method):
  • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
  • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.
• The complaint’s general allegations suggest it reserves the right to assert additional independent and dependent claims.

III. The Accused Instrumentality

Product Identification

• The complaint refers to the accused instrumentalities as "Exemplary Defendant Products" identified in charts within Exhibit 2 (Compl. ¶¶11, 13).

Functionality and Market Context

• The complaint does not provide sufficient detail for analysis of the accused products' specific features, functions, or market context. It alleges generally that the "Exemplary Defendant Products practice the technology claimed by the '960 Patent" but provides no specific product names or descriptions of their operation in the body of the complaint (Compl. ¶13). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges that infringement is detailed in claim charts provided as Exhibit 2 (Compl. ¶¶13-14). As this exhibit was not available for analysis, a claim chart table cannot be constructed. The complaint’s narrative theory is that the "Exemplary Defendant Products practice the technology claimed by the '960 Patent" and "satisfy all elements of the Exemplary '960 Patent Claims" (Compl. ¶13).

Identified Points of Contention

Based on the patent’s claims and the general nature of the allegations, several points of contention may arise.

• Scope Questions: A central question will be whether the architecture of the accused products falls within the scope of the claims. For example, does the mechanism for power saving in the accused products rely on independently controllable "periphery array circuits" for distinct "sections" of a memory array, as recited in the claims? The definition of these terms will be critical.
• Technical Questions: The infringement analysis may turn on specific technical evidence. For instance, what evidence does Plaintiff possess that the accused products use a "programmable address signal" to determine which memory sections to refresh, as required by Claim 1? The case may hinge on whether the accused products' partial-refresh feature is truly programmable or is implemented via a different, non-programmable mechanism.

V. Key Claim Terms for Construction

The Term: "periphery array circuits"

• Context and Importance: This term appears in the dispositive final step of independent claim 1 and is central to the invention's power-saving mechanism. The infringement analysis will depend on whether the circuitry in the accused products that supports memory access qualifies as "periphery array circuits" that are controlled independently per memory section.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification does not provide a single, formal definition, instead referring to them functionally as circuitry configured to "access the memory cells" ('960 Patent, col. 3:25-27). This may support a construction covering any support circuitry that enables read, write, or refresh operations for a section of memory.
  • Evidence for a Narrower Interpretation: Claim 5, which depends from claim 1, explicitly lists circuits that comprise the "periphery array circuits," including "sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" ('960 Patent, col. 8:63-68). A party could argue this list limits the term’s scope. Figure 5 further provides a detailed schematic of these specific circuits, potentially narrowing the term to that disclosed embodiment (160, 162, 164, 166).

The Term: "programmable address signal"

• Context and Importance: This term, recited in Claim 1, specifies the input that initiates the selective background operation. Infringement will require proof that the accused products' partial-refresh feature is controlled by a signal that is "programmable."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term itself is not explicitly defined, which may support a broader reading that includes any signal that can be set or altered to select which memory sections are refreshed, even if configured only once at system startup.
  • Evidence for a Narrower Interpretation: The specification describes a specific embodiment where a "refresh address register" (138) is configured to store a "refresh block address" (AR1) in response to a LOAD signal ('960 Patent, col. 4:55-62; Fig. 3). A party could argue that "programmable" requires a dedicated register that can be loaded with different address values to control the refresh scope, rather than a fixed or hard-wired selection.

VI. Other Allegations

Willful Infringement

• The complaint does not contain an explicit count or allegation of willful infringement. However, the prayer for relief requests a judgment that the "case be declared exceptional within the meaning of 35 U.S.C. § 285" and an award of attorney’s fees (Compl. ¶E.i). No specific facts are alleged in the complaint to support this request.

VII. Analyst’s Conclusion: Key Questions for the Case

Given the limited detail in the complaint, the dispute will likely focus on fundamental issues of claim scope and evidence of infringement that will be developed during discovery.

• A core issue will be one of definitional scope: can the term "periphery array circuits," as detailed in the patent’s specific embodiments, be construed broadly enough to read on the power-saving architecture implemented in the accused products?
• A key evidentiary question will be one of technical implementation: what proof can be adduced to show that the accused products' partial-refresh operations are controlled by a "programmable address signal," as claimed, versus a hard-coded or otherwise non-programmable system? The answer will determine whether a critical limitation of the asserted claims is met.