InnoMemory LLC v. Xiaomi Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Xiaomi Corporation (Cayman Islands)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00667, E.D. Tex., 08/13/2024
• Venue Allegations: Venue is asserted on the basis that the defendant is a foreign corporation.
• Core Dispute: Plaintiff alleges that Defendant infringes a patent related to methods for reducing power consumption in memory devices during refresh operations.
• Technical Context: The technology concerns power-saving techniques for dynamic random-access memory (DRAM), a critical component in mobile and battery-powered devices where standby power consumption is a key performance metric.
• Key Procedural History: The complaint does not mention any prior litigation, IPR proceedings, or licensing history related to the patent-in-suit.

Case Timeline

Date	Event
2002-03-04	Priority Date for U.S. Patent No. 7,057,960
2003-07-29	Application Date for U.S. Patent No. 7,057,960
2006-06-06	Issue Date for U.S. Patent No. 7,057,960
2024-08-13	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

• Patent Identification: U.S. Patent No. 7,057,960, "Method and architecture for reducing the power consumption for memory devices in refresh operations," issued June 6, 2006.

The Invention Explained

• Problem Addressed: The patent’s background section notes that in conventional dynamic semiconductor memory devices, all memory cells are typically refreshed to retain data, even in standby modes where only a portion of the data may be needed. This process consumes significant power because the support circuitry ("periphery array circuits") for all memory sections is activated, which is inefficient for battery-powered devices like portable telephones (’960 Patent, col. 1:35-56). A specific disadvantage noted is that conventional systems activate the periphery circuits for all four memory quadrants even when less than the full array requires refreshing (col. 2:25-29).
• The Patented Solution: The invention proposes a method and architecture to reduce this power consumption by selectively controlling background operations, such as refresh, on a section-by-section basis within the memory array (’960 Patent, Abstract). The system uses specific control signals (e.g., REF0-REFn) to enable the periphery array circuits only for the memory sections designated for refresh, while leaving the circuits for other sections disabled (’960 Patent, col. 3:26-33; Fig. 3). This targeted activation is controlled by a programmable address signal, allowing for flexible partial-array refresh operations (’960 Patent, col. 8:1-4).
• Technical Importance: This approach allows memory systems in devices with low-power standby modes to significantly reduce current draw by refreshing only essential data, directly impacting and extending battery life (’960 Patent, col. 1:31-35).

Key Claims at a Glance

• The complaint does not identify specific claims, instead referring to the “Exemplary ’960 Patent Claims” contained in a non-proffered exhibit (Compl. ¶11). Independent claim 1 is representative:
• Independent Claim 1:
  • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals,
  • wherein said one or more control signals are generated in response to a programmable address signal,
  • and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
  • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.

III. The Accused Instrumentality

Product Identification

The complaint does not identify any specific accused products, services, or methods by name (Compl. ¶11). It refers generally to "Exemplary Defendant Products" that are purportedly identified in "charts" attached as Exhibit 2, but this exhibit was not provided with the filed complaint (Compl. ¶13).

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the accused instrumentality's functionality or market context.

IV. Analysis of Infringement Allegations

The complaint references claim charts in an exhibit that was not provided, and contains no narrative infringement theory in the body of the complaint itself (Compl. ¶13-14). The pleading alleges only that the "Exemplary Defendant Products practice the technology claimed by the '960 Patent" and "satisfy all elements of the Exemplary '960 Patent Claims" (Compl. ¶13). Consequently, a detailed analysis of the infringement allegations is not possible based on the provided documents. No probative visual evidence provided in complaint.

Identified Points of Contention

Given the lack of specific allegations, any infringement analysis will depend entirely on evidence developed during discovery. The central technical questions will likely revolve around the architecture of the accused products' memory controllers and DRAM. Key points of contention may include:

• Architectural Question: Do the accused products’ memory systems contain distinct "periphery array circuits" for different "sections" of a memory array, and can these circuits be independently enabled or disabled for background operations like refresh?
• Control Signal Question: What evidence demonstrates that the accused products use a "programmable address signal" to generate the specific control signals that selectively enable these periphery circuits, as required by the claims?

V. Key Claim Terms for Construction

The Term: "periphery array circuits"

• Context and Importance: This term defines the specific circuitry that the patent claims to control selectively. Infringement will depend on whether the accused products' memory architecture contains structures that meet this definition. Practitioners may focus on this term because its scope will determine whether general power management circuitry falls within the claim, or if a more specific structure is required.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent states these circuits are "configured to access the memory cells" (col. 3:24-25), which could be argued to encompass any access-related circuitry.
  • Evidence for a Narrower Interpretation: The patent explicitly lists components comprising these circuits: "sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" (’960 Patent, col. 7:64-col. 8:1). This enumeration may be used to argue for a narrower construction limited to these specific types of circuits.

The Term: "programmable address signal"

• Context and Importance: This term is central to the invention's method of selecting which memory sections to refresh. The dispute will likely focus on what level of "programmability" is required.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term itself suggests any signal that can be set or changed by a user or system to designate an address, which could be interpreted broadly.
  • Evidence for a Narrower Interpretation: The specification links this signal to information "stored in a refresh address register" that defines the "block address" for the portion of the array to be refreshed (’960 Patent, col. 8:1-4). This may support an argument that the term requires a specific register-based implementation for programming the refresh scope.

VI. Other Allegations

• Indirect Infringement: The complaint does not contain any factual allegations to support a claim for indirect infringement.
• Willful Infringement: The complaint makes no allegations regarding pre- or post-suit knowledge of the patent to support a claim for willful infringement. The prayer for relief includes a request for a declaration that the case is exceptional, but the body of the complaint provides no factual basis for such a finding (Compl. p. 4).

VII. Analyst’s Conclusion: Key Questions for the Case

The initial phase of this case will likely be defined by the complaint's lack of specificity. The central questions that emerge are:

1. An Evidentiary Question: First and foremost, what are the accused products and what is their specific memory management architecture? Without this fundamental information, which the complaint fails to provide, no substantive legal or technical analysis is possible.
2. A Definitional Scope Question: Assuming accused products are identified, a core issue will be whether their power-saving features operate by selectively enabling and disabling discrete "periphery array circuits" in response to a "programmable address signal," as those terms are understood in the context of the ’960 Patent specification.
3. A Functional Question: Does the control mechanism in the accused products perform the specific function of enabling background operations (like refresh) in two or more memory sections "independently of any other section," or does it use a different, more generalized power-gating or clock-gating technique that is architecturally distinct from the patented method?