DCT

2:24-cv-00671

InnoMemory LLC v. Datalogic Spa

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:24-cv-00671, E.D. Tex., 12/10/2024
  • Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because the Defendant is a foreign corporation.
  • Core Dispute: Plaintiff alleges that Defendant infringes a patent related to methods for reducing power consumption in semiconductor memory devices by selectively refreshing only certain portions of the memory array.
  • Technical Context: The technology addresses power efficiency in dynamic random-access memory (DRAM), a critical consideration for extending battery life in mobile and portable electronic devices.
  • Key Procedural History: The patent-in-suit is a continuation of a prior application that issued as U.S. Patent No. 6,618,314. The complaint does not mention any other prior litigation, licensing history, or administrative proceedings related to the patent.

Case Timeline

Date Event
2002-03-04 '960 Patent Earliest Priority Date (filing of parent app.)
2003-07-29 '960 Patent Application Filing Date
2006-06-06 '960 Patent Issue Date
2024-12-10 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - “Method and architecture for reducing the power consumption for memory devices in refresh operations,” issued June 6, 2006

The Invention Explained

  • Problem Addressed: The patent describes a problem with conventional dynamic semiconductor memory (DRAM), particularly in battery-powered devices. In standby mode, even if only a small portion of memory contains data that must be retained, the entire memory array is typically refreshed. This process involves activating support circuitry for all sections of the memory, which consumes significant power and reduces standby time (’960 Patent, col. 1:36-55, col. 2:25-32).
  • The Patented Solution: The invention proposes a method and architecture to reduce this power consumption. The solution involves dividing the memory array into multiple sections (e.g., quadrants) and providing a control circuit that can independently enable or disable the "periphery array circuits"—such as sense amplifiers and wordline drivers—for each section (’960 Patent, Abstract; col. 3:25-32). By using a programmable address signal to select only the specific sections needing a data refresh, the power-consuming support circuits for the other sections remain inactive, thereby saving power (’960 Patent, col. 4:51-54, col. 6:14-22). Figure 3 illustrates this architecture, showing control signals (REF0-REF3) directed to individual memory quadrants (124a-124d).
  • Technical Importance: This approach allows for more granular power management in memory systems, directly addressing the market demand for lower power consumption and longer battery life in the growing portable device sector (’960 Patent, col. 1:31-35).

Key Claims at a Glance

  • The complaint does not identify specific claims, instead referring to "Exemplary '960 Patent Claims" contained in an external exhibit not attached to the pleading (Compl. ¶11, 13). Independent claim 1 is representative of the patent's core method.
  • Independent Claim 1 (Method):
    • Controlling background operations (e.g., refresh) in each of a plurality of memory array sections in response to one or more control signals.
    • The control signals are generated in response to a programmable address signal.
    • The background operations can be enabled simultaneously in two or more sections "independently of any other section."
    • Presenting the control signals and decoded address signals to "one or more periphery array circuits" of the sections.
  • The complaint does not explicitly reserve the right to assert dependent claims but refers generally to infringement of "one or more claims" (Compl. ¶11).

III. The Accused Instrumentality

Product Identification

  • The complaint does not name any specific accused products. It refers only to "Exemplary Defendant Products" that are purportedly identified in "the charts of Exhibit 2" (Compl. ¶13). This exhibit was not filed with the complaint.

Functionality and Market Context

  • The complaint does not provide sufficient detail for analysis of the accused instrumentality's functionality or market context. All substantive allegations regarding the accused products are incorporated by reference from the un-provided Exhibit 2 (Compl. ¶13-14). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint’s infringement allegations are made entirely by incorporating by reference "charts comparing the Exemplary '960 Patent Claims to the Exemplary Defendant Products" in an exhibit that was not provided with the filed complaint (Compl. ¶13-14). The pleading itself contains no specific factual allegations mapping claim elements to accused product features. The narrative theory is limited to the conclusory statement that "the Exemplary Defendant Products practice the technology claimed by the '960 Patent" (Compl. ¶13). Without the referenced exhibit or more detailed pleading, a claim chart summary cannot be constructed.

  • Identified Points of Contention: Based on the language of representative Claim 1 and the general nature of the technology, the dispute may center on the following questions:
    • Architectural Questions: Does the architecture of the accused products feature distinct "periphery array circuits" that correspond to specific, separable sections of a memory array? The infringement case hinges on demonstrating that the accused products contain the specific modular hardware structure described in the patent.
    • Functional Questions: What evidence demonstrates that the accused products can enable background operations (like refresh) in some memory sections while leaving the corresponding periphery circuits for other sections disabled, as required by the "independently of any other section" limitation (’960 Patent, col. 12:38-39)? The complaint provides no facts on this point.

V. Key Claim Terms for Construction

  • The Term: "periphery array circuits"

  • Context and Importance: This term defines the specific hardware that the invention controls to save power. The existence and independent controllability of these circuits in the accused products will be a central issue. Practitioners may focus on this term because its scope—whether limited to the patent's specific examples or covering any functionally similar support logic—is critical to the infringement analysis.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The patent states these circuits "each comprise one or more circuits from the group consisting of sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" (’960 Patent, col. 11:63-67, Claim 5). A party might argue this non-exclusive list defines a functional category rather than a specific structure.
    • Evidence for a Narrower Interpretation: A party could argue the term is limited by the detailed schematics shown, for example, in Figure 5, which illustrates a specific implementation with a network of AND and OR gates (170-189) controlling the wordlines and equalization transistors (’960 Patent, Fig. 5).

  • The Term: "programmable address signal"

  • Context and Importance: This term defines the input that triggers the selective power-saving feature. Infringement will depend on whether the mechanism used in the accused products to select memory sections for refresh qualifies as a "programmable address signal."

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification describes this signal as "information (e.g., a block address) stored in a refresh address register" that controls which portion of the array is refreshed (’960 Patent, col. 8:1-3). This could be argued to encompass any configurable software flag or setting that dictates the refresh scope.
    • Evidence for a Narrower Interpretation: Claim 27 links the signal directly to a "register configured to store said one or more block address signals" (’960 Patent, col. 12:65-67). A party could argue this requires a specific hardware register that stores a literal address, not just a general configuration bit or operational mode setting.

VI. Other Allegations

  • Willful Infringement: The complaint does not allege willful infringement or plead any facts related to pre-suit or post-suit knowledge of the patent by the Defendant. The prayer for relief includes a request that the case be declared "exceptional" under 35 U.S.C. § 285, but provides no factual basis to support such a finding (Compl. ¶E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. An Evidentiary Question of Fact: The central issue is whether the Plaintiff can produce evidence to substantiate the bare allegations in its complaint. Given the complete reliance on an un-provided exhibit, the case will turn on whether discovery reveals that the accused products actually contain the specific, independently controllable "periphery array circuits" for distinct memory sections as required by the patent’s claims.
  2. A Definitional Question of Scope: A core legal issue will be the construction of "periphery array circuits". The outcome of the case may depend on whether this term is interpreted broadly to cover any functionally equivalent power-saving memory architecture, or narrowly to the specific circuit implementations and logic gate arrangements detailed in the patent’s figures and specification.
  3. A Pleading Sufficiency Question: An initial question for the court may be whether the complaint, which outsources all of its substantive infringement allegations to an external, un-filed document, meets the plausibility pleading standards established by Twombly and Iqbal. The Defendant may challenge the complaint for failing to provide adequate notice of the factual basis for the infringement claim.