InnoMemory LLC v. NXP Ap Memory Technology Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: NXP (AP Memory Technology Corp) (Taiwan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00672, E.D. Tex., 08/14/2024
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant is a foreign corporation and has committed acts of patent infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant infringes a patent related to methods and architectures for reducing power consumption in memory devices during refresh operations.
• Technical Context: The technology addresses power management in semiconductor memory, a critical factor for extending battery life in portable electronic devices.
• Key Procedural History: The asserted patent is a continuation of a prior application, U.S. Ser. No. 10/090,850, which issued as U.S. Patent No. 6,618,314. This prosecution history may be relevant for claim construction and potential estoppel arguments.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - Method and architecture for reducing the power consumption for memory devices in refresh operations

Issued: June 6, 2006

The Invention Explained

• Problem Addressed: The patent addresses the problem of high power consumption in dynamic random access memories (DRAMs) during standby or reduced power modes (Compl. Ex. 1, '960 Patent, col. 1:36-48). Conventional DRAMs refresh all memory cells, but many applications, particularly in battery-powered devices, only need to retain data in a portion of the memory. The patent notes a specific disadvantage of conventional systems is that "the periphery array circuits of all four quadrants are activated when less than the full array...requires refreshing," leading to unnecessary power draw (Compl. Ex. 1, '960 Patent, col. 2:26-29).
• The Patented Solution: The invention proposes an architecture where a memory array is divided into multiple sections (e.g., quadrants). A control circuit can selectively perform background operations, like data refresh, on one or more of these sections independently. This is accomplished by generating control signals that enable the "periphery array circuitry" (such as drivers and sense amplifiers) only for the sections being refreshed, while leaving the circuitry for other sections inactive, thereby reducing overall power consumption (Compl. Ex. 1, '960 Patent, col. 3:25-33; col. 5:6-23). This selection is controlled by a "programmable address signal," which allows the system to define which portion of the memory needs to be actively maintained (Compl. Ex. 1, '960 Patent, claim 1).
• Technical Importance: This approach allows for more granular power management in memory systems, which is critical for extending the operational time of battery-powered mobile devices like portable telephones (Compl. Ex. 1, '960 Patent, col. 1:40-44).

Key Claims at a Glance

• The complaint asserts infringement of "one or more claims" without specifying them, instead referring to "Exemplary '960 Patent Claims" in an unattached exhibit (Compl. ¶11). The independent claims of the '960 Patent are claims 1, 9, 10, 26, and 27. An analysis of independent apparatus claim 10 follows:
• Independent Claim 10 (Apparatus):
  • A memory array comprising a plurality of sections, wherein each of said sections comprises (i) a plurality of memory cells and (ii) periphery array circuitry configured to control access to said plurality of memory cells; and
  • a control circuit configured to present one or more control signals and one or more decoded address signals to said periphery array circuitry of said plurality of sections,
  • wherein said one or more control signals are generated in response to a programmable address signal,
  • a background operation in each of said plurality of sections is controlled in response to said one or more control signals and
  • said background operation can be enabled simultaneously in two or more of said plurality of sections independently of any other section.
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

• The complaint does not name any specific accused products. It refers generally to "Exemplary Defendant Products" that are purportedly identified in charts within Exhibit 2 (Compl. ¶11, ¶13). However, Exhibit 2 was not filed with the complaint.

Functionality and Market Context

• The complaint does not provide sufficient detail for analysis of the accused products' functionality or market context. It alleges only that the "Exemplary Defendant Products practice the technology claimed by the '960 Patent" (Compl. ¶13). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges direct infringement but relies entirely on claim charts in an unattached "Exhibit 2" to provide the basis for this allegation (Compl. ¶13-14). The narrative infringement theory is conclusory, stating that "the Exemplary Defendant Products incorporated in these charts satisfy all elements of the Exemplary '960 Patent Claims" (Compl. ¶13). Without the referenced exhibit, a detailed, element-by-element analysis of the infringement allegations is not possible.

Identified Points of Contention

• Based on the patent claims, any future infringement analysis will likely focus on several key technical and scope questions.
  • Scope Questions: A central question will be whether the power-saving modes in the accused products function by selectively enabling and disabling "periphery array circuitry" for distinct "sections" of a memory array, as those terms are defined by the patent. The definition of what constitutes a "section" and its associated "periphery array circuitry" may be a point of dispute.
  • Technical Questions: A key evidentiary issue will be whether the accused products utilize a "programmable address signal" to determine which memory sections remain active during low-power states. The complaint provides no facts regarding the specific mechanism used by Defendant's products to control partial array refresh operations.

V. Key Claim Terms for Construction

• The Term: "periphery array circuitry" (claim 10)

• Context and Importance: This term is central to the invention's power-saving mechanism. The infringement analysis will depend on whether the accused products contain structures that meet this definition. Practitioners may focus on this term because its scope determines whether the claims read on modern power-gating techniques that may differ from the specific circuits disclosed.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The term itself is generic. Claim 5 further defines the circuitry as comprising "one or more circuits from the group consisting of sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" (Compl. Ex. 1, '960 Patent, col. 7:60-col. 8:1). A party might argue this list is exemplary, not exhaustive.
  • Evidence for a Narrower Interpretation: The specification provides specific circuit diagrams for these components (e.g., FIG. 5). A party might argue that "periphery array circuitry" should be limited to the types of circuits disclosed and their structural arrangement for accessing memory cells within a section.

• The Term: "programmable address signal" (claim 10)

• Context and Importance: This signal is the input that controls which memory sections are selected for background operations. The "programmable" nature of the signal is a key limitation. The dispute may turn on whether the control mechanism in the accused products can be characterized as being responsive to a "programmable address signal."

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The claim language itself does not specify the mechanism of programmability. A party could argue it covers any signal that can be configured or set by a user or system to select different combinations of memory sections.
  • Evidence for a Narrower Interpretation: The specification discloses a specific implementation where a "refresh address register" (138) stores a "refresh block address" (REF_BLK) that is loaded into the register (Compl. Ex. 1, '960 Patent, col. 4:55-62; FIG. 3). A party could argue that "programmable" requires a dedicated, loadable register as shown in the preferred embodiments.

VI. Other Allegations

Willful Infringement

• The complaint does not plead any specific facts to support a claim of willful infringement, such as pre-suit knowledge of the patent or egregious conduct. However, the prayer for relief requests a finding that the case is "exceptional" under 35 U.S.C. § 285, which is the statutory basis for awarding enhanced damages and attorney fees, often in cases of willful infringement (Compl. p. 4, ¶E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

Given the limited information in the complaint, the case currently presents foundational evidentiary and legal questions.

1. A threshold evidentiary question is what specific products are accused of infringement and what technical evidence Plaintiff will offer to show that they operate in the manner required by the claims. This information is absent from the public filing.

2. A core issue will be one of definitional scope: can the term "periphery array circuitry," as described in the patent's 2002-era context, be construed to cover the specific power management circuits used in Defendant's modern memory products?

3. The case will likely involve a key technical-legal question regarding claim construction: does the control mechanism in the accused products meet the "programmable address signal" limitation, or does it use a different, non-infringing method to select portions of memory for low-power operation?