InnoMemory LLC v. Acrosser Technology Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Acrosser Technology Co. Ltd (Taiwan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00678, E.D. Tex., 08/19/2024
• Venue Allegations: Venue is alleged to be proper on the basis that the defendant is a foreign corporation.
• Core Dispute: Plaintiff alleges that Defendant’s unidentified memory products infringe a patent related to methods for reducing power consumption in memory devices during refresh operations.
• Technical Context: The technology concerns power-saving techniques for dynamic random-access memory (DRAM), a critical component in extending battery life for portable electronic devices.
• Key Procedural History: The patent-in-suit is a continuation of a prior application, U.S. Ser. No. 10/090,850, which issued as U.S. Patent No. 6,618,314. No other procedural history is mentioned in the complaint.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - “Method and architecture for reducing the power consumption for memory devices in refresh operations”

• Patent Identification: U.S. Patent No. 7,057,960 (“Method and architecture for reducing the power consumption for memory devices in refresh operations”), issued June 6, 2006.

The Invention Explained

• Problem Addressed: The patent describes a problem with conventional dynamic semiconductor memory devices (DRAMs), particularly in battery-powered applications like portable terminals. In standby mode, these devices consume significant power by refreshing all memory cells, even if only a portion of the memory contains data that needs to be retained. Furthermore, conventional partial-refresh schemes still activate the support circuitry for all sections of the memory array, which is inefficient. (’960 Patent, col. 1:31-56, col. 2:25-30).
• The Patented Solution: The invention proposes a method and architecture to reduce this power consumption by selectively activating only the necessary circuitry. The system uses control signals to enable or disable the "periphery array circuits" (e.g., sense amplifiers, wordline drivers) corresponding to specific sections of the memory array. This allows the device to refresh only the required memory sections while keeping the support circuitry for all other sections powered down. (’960 Patent, Abstract; col. 3:20-33). Figure 3 illustrates this concept, showing a control circuit (102) generating distinct refresh signals (REF0-REF3) for different memory quadrants (124a-124d).
• Technical Importance: This approach aimed to reduce standby power requirements for memory devices, thereby extending the operational time of battery-powered electronics, a key concern in the growing mobile device market. (’960 Patent, col. 1:37-47).

Key Claims at a Glance

• The complaint does not specify which claims are asserted, referring only to "Exemplary '960 Patent Claims" within an unprovided exhibit (Compl. ¶11, ¶13). Claim 1 is the first independent method claim.
• The essential elements of independent Claim 1 include:
  • A method for reducing power consumption during background operations in a memory array having multiple sections.
  • Controlling the background operations in each section using one or more control signals.
  • Generating these control signals in response to a "programmable address signal."
  • The background operations can be enabled simultaneously in two or more sections, independently of any other section.
  • Presenting the control signals and decoded address signals to the "periphery array circuits" of the sections.
• The complaint does not explicitly reserve the right to assert other claims, but its vague reference to "one or more claims" suggests this possibility (Compl. ¶11).

III. The Accused Instrumentality

Product Identification

• The complaint does not identify any specific accused products by name. It refers generally to "Defendant products identified in the charts incorporated into this Count below" and "Exemplary Defendant Products" (Compl. ¶11, ¶13). The referenced charts in Exhibit 2 were not filed with the complaint.

Functionality and Market Context

• The complaint provides no description of the accused products' functionality, technical operation, commercial importance, or market positioning. It makes only the conclusory allegation that the products "practice the technology claimed by the '960 Patent" (Compl. ¶13). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint's infringement theory is contained entirely within "charts of Exhibit 2," which it incorporates by reference (Compl. ¶14). As this exhibit was not provided, a detailed element-by-element analysis is not possible.

The narrative allegations are conclusory, stating that Defendant’s unidentified products "satisfy all elements of the Exemplary '960 Patent Claims" (Compl. ¶13). The complaint does not offer a prose-based description of how any accused product meets any specific claim limitation.

• Identified Points of Contention: Given the absence of factual allegations, any potential dispute is speculative. However, based on the patent's claims, key questions will likely involve:
  • Factual Question: The central issue will be whether Plaintiff can produce evidence that any of Defendant's products practice the claimed method. This includes demonstrating the presence of distinct memory sections with corresponding "periphery array circuits" that are selectively and independently controlled.
  • Scope Question: A dispute may arise over the meaning of "background operations." While the patent focuses on refresh operations (Claim 2), it also mentions "parity checking" (Claim 4), raising the question of whether the claims are limited to refresh cycles or encompass other low-power maintenance tasks.

V. Key Claim Terms for Construction

• The Term: "periphery array circuits" (from Claim 1)

• Context and Importance: This term is central to the invention's power-saving mechanism. Infringement hinges on identifying these specific circuits within an accused device and proving they are selectively enabled or disabled for different memory sections. The definition of what constitutes a "periphery array circuit" will be critical.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: A party might argue for a functional definition, covering any support circuitry associated with a memory section that is activated during access. The specification provides a non-exhaustive list of examples, which may suggest the term is not limited to those examples alone (’960 Patent, col. 7:20-24, col. 11:63-68).
  • Evidence for a Narrower Interpretation: A party could argue the term is limited to the specific circuits disclosed in the patent, such as the "sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" enumerated in dependent Claim 5 (’960 Patent, col. 11:65-68). The detailed schematics in Figure 5, which show specific logic-gate implementations for these functions, could be used to argue for a more structurally limited definition.

• The Term: "programmable address signal" (from Claim 1)

• Context and Importance: This signal is the input that dictates which memory sections are subject to the "background operation." The nature and source of this signal are key to determining how the selective refresh is controlled and whether an accused device meets this limitation.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The term could be construed broadly to mean any signal that can be set by a system to designate a portion of memory for a background operation. The patent describes this signal as "information (e.g., a block address) stored in a refresh address register" (’960 Patent, col. 8:1-4), which could encompass a wide range of software- or hardware-based configuration methods.
  • Evidence for a Narrower Interpretation: The interpretation could be narrowed to the specific implementation shown in the patent's figures, where a "refresh address register 138" is explicitly loaded to generate "REF_BLK" signals that control the refresh (’960 Patent, FIG. 3; col. 4:56-65). This might require the signal to originate from a dedicated, hardware-based register as depicted.

VI. Other Allegations

• Willful Infringement: The complaint does not contain an explicit allegation of willful infringement. However, in the prayer for relief, Plaintiff requests that the case be declared "exceptional within the meaning of 35 U.S.C. § 285" (Compl. p. 4). The complaint pleads no specific facts, such as pre-suit knowledge of the patent, to support this request.

VII. Analyst’s Conclusion: Key Questions for the Case

1. A threshold issue will be one of factual sufficiency: The complaint is devoid of factual allegations identifying an accused product or explaining the basis for infringement. A primary question is whether Plaintiff can substantiate its conclusory claims with evidence sufficient to survive a motion to dismiss and proceed to discovery.

2. A core technical dispute will likely concern structural and functional correspondence: Assuming an accused product is identified, the case will turn on whether that product’s architecture maps onto the patent’s claims. This will involve determining if the product contains distinct "periphery array circuits" that are independently controlled for different memory sections in response to a "programmable address signal," or if its power-saving mechanism operates in a fundamentally different way.