DCT

2:24-cv-00679

InnoMemory LLC v. NEXCOM Intl Co Ltd

Key Events
Complaint
complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:24-cv-00679, E.D. Tex., 08/19/2024
  • Venue Allegations: Venue is alleged to be proper as the Defendant is a foreign corporation.
  • Core Dispute: Plaintiff alleges that Defendant’s memory devices infringe a patent related to methods for reducing power consumption during memory refresh operations.
  • Technical Context: The technology concerns power-saving techniques in dynamic random-access memory (DRAM), which is critical for extending battery life in portable electronic devices.
  • Key Procedural History: The patent-in-suit is a continuation of an earlier U.S. patent application. The complaint does not mention any prior litigation, inter partes review (IPR) proceedings, or licensing history related to the patent.

Case Timeline

Date Event
2002-03-04 Earliest Priority Date ('960 Patent)
2003-07-29 Application Filing Date ('960 Patent)
2006-06-06 Issue Date for U.S. Patent No. 7,057,960
2024-08-19 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

  • Issued: June 6, 2006

The Invention Explained

  • Problem Addressed: The patent describes a problem in conventional dynamic semiconductor memory devices, particularly those used in battery-powered portable terminals. These devices traditionally refresh all memory cells to prevent data loss, even when only a portion of the memory contains data that needs to be retained in a low-power standby mode. This process activates all associated "periphery array circuits," consuming significant and often unnecessary power, which reduces battery life (ʼ960 Patent, col. 2:26-36).
  • The Patented Solution: The invention proposes a method and architecture to reduce this power consumption by selectively refreshing only the necessary sections of the memory array. This is achieved by using control signals, generated in response to a "programmable address signal," to enable the periphery circuits for only those memory sections being actively refreshed, while leaving the circuits for other sections inactive (ʼ960 Patent, col. 2:37-44, 2:50-54). Figure 3 illustrates a control circuit (102) that generates specific refresh signals (REF0-REF3) to control individual memory quadrants (124a-124d), thereby localizing power use during a refresh operation (ʼ960 Patent, Fig. 3).
  • Technical Importance: This approach was aimed at addressing the market demand for memory devices with lower standby power consumption, a critical factor for improving the continuous standby time of mobile devices like portable telephones (ʼ960 Patent, col. 2:30-36, 2:52-55).

Key Claims at a Glance

The complaint does not identify the specific claims asserted but refers to "Exemplary '960 Patent Claims" (Compl. ¶11). The patent’s lead independent claims are Method Claim 1 and Apparatus Claim 10.

  • Independent Claim 1 (Method):

    • controlling background operations in each of a plurality of sections of a memory array in response to one or more control signals;
    • wherein the control signals are generated in response to a programmable address signal;
    • wherein the background operations can be enabled simultaneously in two or more sections independently of any other section; and
    • presenting the control signals and one or more decoded address signals to one or more periphery array circuits of the sections.
  • Independent Claim 10 (Apparatus):

    • a memory array comprising a plurality of sections, each having memory cells and periphery array circuitry;
    • a control circuit configured to present control signals and decoded address signals to the periphery array circuitry;
    • wherein the control signals are generated in response to a programmable address signal; and
    • a background operation in each section is controlled by the control signals and can be enabled simultaneously in two or more sections independently of any other section.

III. The Accused Instrumentality

Product Identification

The complaint refers to "Exemplary Defendant Products" but does not name any specific products, models, or product families (Compl. ¶11). It states that these products are identified in charts within an "Exhibit 2" which is referenced but not attached to the publicly filed complaint (Compl. ¶13).

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the accused instrumentality's functionality or market context. It makes only a general allegation that the products "practice the technology claimed by the '960 Patent" (Compl. ¶13).

IV. Analysis of Infringement Allegations

The complaint alleges that Defendant directly infringes the ’960 Patent by making, using, selling, or importing the "Exemplary Defendant Products" (Compl. ¶11). The pleading states that infringement is detailed in claim charts provided in an Exhibit 2 (Compl. ¶13). As this exhibit was not included with the complaint, a detailed claim chart summary cannot be constructed. The narrative infringement theory is that the accused products contain all the elements of the asserted claims (Compl. ¶13).

No probative visual evidence provided in complaint.

Identified Points of Contention

  • Evidentiary Questions: A primary issue will be establishing the specific functionality of the accused products, given the lack of detail in the complaint. Discovery will be required to determine how Defendant's products manage memory refresh cycles and power consumption.
  • Technical Questions: A key question will be whether the accused products perform "background operations" that are "enabled simultaneously in two or more... sections independently," as required by the claims. The analysis will focus on whether the products' power management for memory involves selectively activating and deactivating periphery circuits for distinct memory sections based on a programmable signal.

V. Key Claim Terms for Construction

"background operations"

  • Context and Importance: This term appears in both independent claims 1 and 10. While the patent specification heavily emphasizes "refresh operations" as the primary example of a background operation, dependent claims also mention "parity checking" (ʼ960 Patent, Claim 2, Claim 4). Practitioners may focus on this term because the scope of infringement could depend on whether it is construed narrowly to mean only refresh operations or more broadly to include other types of automated, non-user-facing memory management tasks.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: Claim 2 states the method of claim 1, "wherein said background operations comprise a refresh operation," and Claim 4 states it "comprise parity checking." The use of "comprise" suggests these are non-exclusive examples, potentially broadening the term to other similar operations (ʼ960 Patent, col. 11:53-55, col. 11:58-60).
    • Evidence for a Narrower Interpretation: The patent’s title, abstract, and background section consistently and almost exclusively frame the invention in the context of "refresh operations" to solve a power consumption problem in standby mode. A party could argue that this consistent focus limits the scope of "background operations" to this specific context (ʼ960 Patent, Title; Abstract; col. 1:11-14).

"programmable address signal"

  • Context and Importance: This signal is the input that dictates which memory sections are subject to the "background operations." The nature of this "programmable" signal is central to infringement. Practitioners may focus on this term because the dispute may turn on whether a static, one-time configuration in an accused device meets the "programmable" requirement, or if the term requires dynamic, in-field programmability.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes a "refresh address register" that is programmed "with the portion of the memory array . . . to be refreshed," which could be interpreted as a one-time setting stored in a register (ʼ960 Patent, col. 1:65–col. 2:2).
    • Evidence for a Narrower Interpretation: The explicit use of the word "programmable" may suggest a capability that can be altered post-manufacture, as opposed to a fixed or hard-wired configuration. The patent links this signal to a "refresh address register 18," which implies an input that can be modified to control the device's behavior (ʼ960 Patent, col. 2:63-65).

VI. Other Allegations

Willful Infringement

The complaint does not use the term "willful infringement." However, in its prayer for relief, it requests that the case be declared "exceptional within the meaning of 35 U.S.C. § 285" to support an award of attorneys' fees (Compl. p. 4, ¶ E.i). Such a request is typically predicated on allegations of willful infringement or other litigation misconduct. The complaint does not plead any specific facts to support pre-suit or post-suit knowledge of the patent.

VII. Analyst’s Conclusion: Key Questions for the Case

  • Evidentiary Sufficiency: The case's initial phase will be defined by an evidentiary deficit. The complaint's failure to identify any accused products or provide the referenced claim charts leaves the core of the infringement allegation unspecified. A central question is what evidence Plaintiff will produce to connect Defendant's actual products to the claims.
  • Definitional Scope: The dispute will likely involve a question of claim scope: can the term "background operations," which is described primarily in the context of memory refresh, be construed to cover other automated power-saving or memory management functions that may be present in modern memory devices?
  • Technical Equivalence: A key technical question will be one of functional implementation: what mechanism in the accused products, if any, corresponds to the claimed "programmable address signal"? The case may turn on whether the accused devices feature a truly programmable control for selective memory operations or a different, non-infringing power management architecture.