InnoMemory LLC v. Axiomtek Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Axiomtek Co., Ltd. (Taiwan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:24-cv-00681, E.D. Tex., 08/19/2024
• Venue Allegations: Venue is alleged to be proper because the defendant is a foreign corporation, and the complaint asserts that acts of patent infringement occurred within the district.
• Core Dispute: Plaintiff alleges that certain of Defendant’s memory products infringe a patent related to methods and architectures for reducing power consumption in memory devices during refresh operations.
• Technical Context: The technology concerns selectively activating support circuitry for only those portions of a memory array being refreshed, a technique designed to reduce standby power consumption, particularly in battery-powered electronics.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patent-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

• Patent Identification: U.S. Patent No. 7,057,960, "Method and architecture for reducing the power consumption for memory devices in refresh operations," issued June 6, 2006.

The Invention Explained

• Problem Addressed: The patent describes a problem in conventional dynamic random access memories (DRAMs) where, during standby or power-down modes, significant power is consumed because the support circuitry for the entire memory array is activated for refresh operations, even when only a portion of the data needs to be retained (’960 Patent, col. 1:49-56, col. 2:26-29). This is particularly disadvantageous for battery-powered portable devices (’960 Patent, col. 1:36-41).
• The Patented Solution: The invention proposes a memory architecture where the array is divided into multiple sections (e.g., quadrants), each with its own "periphery array circuits" (such as sense amplifiers and drivers). A control circuit can then selectively enable the periphery circuits for only those sections that require a background operation like a refresh, while keeping the circuits for other sections disabled, thereby reducing overall power draw (’960 Patent, col. 2:36-44, col. 4:26-32, Fig. 3). The selection of which sections to refresh is controlled by a programmable address signal (’960 Patent, col. 4:55-65).
• Technical Importance: This selective activation method directly addressed the market demand for lower standby power consumption in the growing mobile device sector of the early 2000s (’960 Patent, col. 1:32-35).

Key Claims at a Glance

The complaint asserts infringement of "one or more claims" without specifying them (Compl. ¶11). The patent's independent claims, such as method claim 1 and apparatus claim 10, appear representative of the core invention.

• Independent Claim 1 (Method):

  • controlling background operations in each of a plurality of sections of a memory array in response to one or more control signals;
  • wherein the control signals are generated in response to a programmable address signal;
  • and the background operations can be enabled simultaneously in two or more sections independently of any other section; and
  • presenting the control signals and decoded address signals to one or more periphery array circuits of the sections.

• Independent Claim 10 (Apparatus):

  • A memory array with a plurality of sections, each comprising memory cells and periphery array circuitry;
  • A control circuit configured to present control signals and decoded address signals to the periphery array circuitry;
  • wherein the control signals are generated in response to a programmable address signal; and
  • a background operation in each section is controlled by the control signals and can be enabled in two or more sections simultaneously and independently.

The complaint does not explicitly reserve the right to assert dependent claims, but its broad reference to "one or more claims" leaves this possibility open (Compl. ¶11).

III. The Accused Instrumentality

Product Identification

• The complaint does not name specific accused products in its text, referring generally to "Exemplary Defendant Products" that are purportedly identified in an exhibit (Compl. ¶11, ¶13).

Functionality and Market Context

• The complaint alleges that the accused products "practice the technology claimed by the '960 Patent" but provides no specific details regarding their architecture, power management features, or operational modes (Compl. ¶13). The complaint does not provide sufficient detail for analysis of the accused instrumentality's functionality.

IV. Analysis of Infringement Allegations

The complaint incorporates by reference its infringement allegations from "Exhibit 2," which was not filed with the complaint (Compl. ¶13, ¶14). As such, a detailed claim chart cannot be constructed from the provided documents. The complaint summarily alleges that the "Exemplary Defendant Products incorporated in these charts satisfy all elements of the Exemplary '960 Patent Claims" (Compl. ¶13).

No probative visual evidence provided in complaint.

• Identified Points of Contention: Based on the patent's claims and the general nature of the dispute, the infringement analysis will likely raise several questions:
  • Scope Questions: A central question will likely be whether the architecture of the accused memory products includes discrete, independently controllable "periphery array circuits" for different sections of the memory array, as required by the claims. The definition of what constitutes such a circuit versus a more integrated power-gating design may be a point of dispute.
  • Technical Questions: It remains to be seen what evidence Plaintiff will present to show that the accused products use "one or more control signals" generated in response to a "programmable address signal" to achieve selective power-down during refresh (’960 Patent, col. 12:15-16), as opposed to utilizing other, potentially non-infringing, power-saving techniques.

V. Key Claim Terms for Construction

• The Term: "periphery array circuits"

  • Context and Importance: This term is foundational to the invention, as selectively enabling and disabling these circuits is the mechanism for power reduction. The infringement case will depend on whether the accused products contain structures that meet this definition.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: Claim 5 explicitly lists circuits from the group "consisting of sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" (’960 Patent, col. 11:63-65). Plaintiff may argue this list is exemplary, not exhaustive, covering any support circuitry outside the core memory cell matrix.
    • Evidence for a Narrower Interpretation: A defendant may argue the term is limited to the specific combination and arrangement of circuits disclosed in the preferred embodiments, such as the distinct driver, equalization, and amplifier blocks shown in Figure 5 (’960 Patent, Fig. 5).

• The Term: "programmable address signal"

  • Context and Importance: This signal is the input that dictates which memory sections are targeted for a background operation. Infringement requires this specific control input, so its definition is critical. Practitioners may focus on this term because it distinguishes the invention from fixed or non-programmable power-saving modes.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The term could be interpreted broadly to mean any signal that can be set or modified by a user or system to select a subset of the memory array for active refresh.
    • Evidence for a Narrower Interpretation: The specification links this concept to a "refresh address register" that stores a "block address" to control which sections are refreshed (’960 Patent, col. 8:1-3, col. 4:55-65). A defendant could argue the term is limited to this specific register-based implementation.

VI. Other Allegations

• Indirect Infringement: The complaint does not contain allegations that would support a claim for indirect (induced or contributory) infringement.
• Willful Infringement: The complaint does not allege facts to support a claim for willful infringement. However, the prayer for relief requests that the court declare the case "exceptional" under 35 U.S.C. § 285, which, if granted, could form a basis for an award of attorney fees (Compl. p. 4, ¶E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of architectural mapping: can Plaintiff demonstrate that the accused memory products contain the specific claimed structure of a memory array divided into sections with corresponding "periphery array circuits" that can be independently and selectively disabled?
• A key evidentiary question will concern the control mechanism: what proof will be offered to show that the accused products use a "programmable address signal" to generate control signals for selective refresh, as distinguished from other, potentially non-infringing, power management schemes?
• An initial procedural question may be the sufficiency of the pleadings. Given the complaint’s reliance on an unfiled exhibit to provide the factual basis for its infringement allegations, the case may face early motions practice regarding whether the pleading standards have been met.