InnoMemory LLC v. BOKF NA

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: BOKF, NA. (Bank of Texas) (Texas)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:25-cv-00110, E.D. Tex., 02/01/2025
• Venue Allegations: Plaintiff alleges venue is proper as Defendant maintains an established place of business in the district and has allegedly committed acts of infringement there.
• Core Dispute: Plaintiff alleges that Defendant's use of certain products containing memory devices infringes a patent related to reducing power consumption during memory refresh operations.
• Technical Context: The technology relates to methods for selectively refreshing portions of a dynamic random-access memory (DRAM) array to reduce power consumption, a critical consideration in mobile devices and large-scale data center hardware.
• Key Procedural History: The patent-in-suit is a continuation of a prior application which issued as U.S. Patent No. 6,618,314, a fact that could be relevant for claim construction and prosecution history analysis. The complaint does not mention any other prior litigation or administrative proceedings involving the patent.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

• Patent Identification: U.S. Patent No. 7,057,960, issued June 6, 2006.

The Invention Explained

• Problem Addressed: The patent addresses the problem of high power consumption in dynamic random access memory (DRAM) devices during standby mode (Compl. ¶9; '960 Patent, col. 1:26-35). Conventional methods often refresh the entire memory array, or, even in partial-refresh schemes, activate the support circuitry (periphery circuits) for all memory sections, which is inefficient and drains power, a particular problem for battery-powered mobile devices ('960 Patent, col. 1:36-48, col. 2:25-29).
• The Patented Solution: The invention proposes a method and architecture for controlling "background operations" like memory refresh for individual sections of a memory array. The system uses control signals generated in response to a "programmable address signal" to enable the periphery array circuits (e.g., sense amplifiers, drivers) only for the specific memory sections being refreshed, while leaving the circuitry for all other sections disabled, thereby reducing overall power draw ('960 Patent, Abstract; col. 2:36-44). The architecture is illustrated in figures such as Figure 3, which depicts a control circuit generating section-specific refresh signals (REF0-REF3) for different quadrants of a memory array ('960 Patent, Fig. 3).
• Technical Importance: This approach aimed to reduce standby power requirements for memory devices, a key factor for improving battery life in the "growing mobile market" of the time ('960 Patent, col. 1:33-35).

Key Claims at a Glance

• The complaint does not identify specific asserted claims, referring generally to "one or more claims" and "Exemplary '960 Patent Claims" in a referenced exhibit that was not provided with the complaint (Compl. ¶11, ¶13). As a representative independent claim, Claim 1 is analyzed below.
• Independent Claim 1:
  • A method for reducing power consumption during background operations in a memory array with a plurality of sections, comprising the steps of:
  • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
  • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.
• The complaint’s general allegations implicitly reserve the right to assert additional independent and dependent claims.

III. The Accused Instrumentality

Product Identification

• The complaint identifies the accused instrumentalities as the "Exemplary Defendant Products" detailed in an incorporated Exhibit 2, which was not provided with the complaint (Compl. ¶11, ¶13).

Functionality and Market Context

• The complaint does not describe the specific functionality or market context of the accused products. It alleges that Defendant, a bank, directly infringes by "making, using, offering to sell, selling and/or importing" the products, and by having its "employees internally test and use" them (Compl. ¶11-12). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references claim charts in an external "Exhibit 2" but does not provide the exhibit itself or plead any specific facts in the body of the complaint mapping accused product features to claim limitations (Compl. ¶13-14). The infringement theory is stated in a conclusory manner, alleging that the "Exemplary Defendant Products practice the technology claimed by the '960 Patent" (Compl. ¶13). Without the referenced charts, a detailed analysis of the infringement allegations is not possible.

• Identified Points of Contention: Based on the patent and the nature of the technology, several points of contention may arise.
  • Scope Questions: The interpretation of "background operations" will be significant. While Claim 2 narrows this to a "refresh operation," the asserted Claim 1 is broader ('960 Patent, col. 11:55-57). The litigation may raise the question of whether the accused processes on the defendant's products constitute "background operations" as contemplated by the patent.
  • Technical Questions: A central technical question will be whether the accused products, likely standard computer hardware, contain memory systems that perform the specific function of selectively enabling and disabling "periphery array circuits" for discrete memory sections. The case may turn on what evidence Plaintiff can produce to show that the accused products’ power-saving features operate in the manner claimed, rather than through a different technical mechanism.

V. Key Claim Terms for Construction

• The Term: "programmable address signal"

• Context and Importance: This signal is the input that allegedly controls which memory sections undergo background operations. The outcome of the infringement analysis depends on whether the accused products utilize a signal that meets this definition. Practitioners may focus on this term because its construction will determine whether standard memory configuration data, set by firmware or software in the accused products, qualifies as a "programmable address signal" under the patent.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent describes controlling the refreshed portion of an array with information like a "block address" stored in a "refresh address register," suggesting that any configurable signal that designates a memory area could fall within the term's scope ('960 Patent, col. 8:1-4).
  • Evidence for a Narrower Interpretation: The preferred embodiment shows a specific hardware implementation where a "refresh address register 138" receives a signal "AR1" from an address buffer and is updated in response to a "LOAD" signal, which could support an argument that the term requires a specific type of dedicated, hardware-based address signal ('960 Patent, Fig. 3; col. 4:55-61).

• The Term: "periphery array circuits"

• Context and Importance: The claimed invention achieves its power-saving benefit by selectively controlling these specific circuits. Infringement requires showing that the accused products not only have these circuits but control them in the claimed manner.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: A dependent claim provides a non-exhaustive list of such circuits, including "sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" ('960 Patent, col. 11:63-65). Plaintiff may argue this list is merely exemplary and that the term covers any ancillary circuitry that supports a section of memory cells.
  • Evidence for a Narrower Interpretation: The detailed description and Figure 5 illustrate a specific circuit layout and combination of these elements, including wordline driver 160, equalization circuit 162, and sense amplifiers 164a-164x ('960 Patent, Fig. 5). Defendant may argue that the term should be limited to the types of circuits and the specific architectural arrangement disclosed in the patent’s embodiments.

VI. Other Allegations

• Willful Infringement: The complaint requests a judgment for enhanced damages under 35 U.S.C. § 284 and a finding that the case is "exceptional" under 35 U.S.C. § 285 (Compl. ¶D, ¶E.i). However, the complaint does not plead any specific facts to support a claim of willful infringement, such as allegations of pre-suit or post-suit knowledge of the patent and its infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

1. Evidentiary Sufficiency: A primary issue is one of evidentiary demonstration. Given the complaint’s lack of specific factual allegations and its reliance on an unprovided exhibit, a key question is what technical evidence Plaintiff will be able to produce to show that the accused products—unidentified hardware used by a financial institution—practice the specific, granular steps of selectively controlling "periphery array circuits" based on a "programmable address signal".

2. Claim Scope and Technical Match: The case will likely involve a core question of claim scope versus modern technology. Can the term "periphery array circuits," as defined by the patent’s 2002-priority-date disclosure, be construed to read on the architecture of the memory controllers and power management units found in the accused systems, or will discovery reveal a fundamental mismatch in technical operation?