InnoMemory LLC v. Newline Interactive Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Newline Interactive Inc. (Delaware)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:25-cv-00119, E.D. Tex., 02/02/2025
• Venue Allegations: Venue is alleged to be proper based on Defendant maintaining an established place of business within the Eastern District of Texas.
• Core Dispute: Plaintiff alleges that unspecified products made by Defendant infringe a patent related to methods for reducing power consumption in memory chips during refresh operations.
• Technical Context: The technology concerns power-saving techniques for dynamic random-access memory (DRAM), a key component in electronic devices where battery life and standby power are critical design considerations.
• Key Procedural History: The patent-in-suit is a continuation of a prior U.S. patent application. The complaint does not mention any other prior litigation, licensing history, or administrative proceedings involving the patent.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

• Patent Identification: U.S. Patent No. 7,057,960, Method and architecture for reducing the power consumption for memory devices in refresh operations, issued June 6, 2006.

The Invention Explained

• Problem Addressed: In conventional dynamic random-access memory (DRAM), maintaining data in standby mode requires periodic "refresh" operations. The patent’s background section notes a key inefficiency: even when only a portion of the memory needs to be retained, the support circuitry (periphery array circuits) for all sections of the memory array is activated, which consumes unnecessary power (’960 Patent, col. 2:27-30). This is particularly disadvantageous for battery-powered mobile devices (’960 Patent, col. 2:30-34).
• The Patented Solution: The invention proposes a method and architecture to make refresh operations more power-efficient. It does so by dividing the memory array into multiple sections and providing a control circuit that can selectively enable or disable the power-consuming periphery array circuits for each section independently (’960 Patent, Abstract). This allows the device to refresh only the necessary sections of memory while keeping the support circuitry for all other sections powered down, thereby reducing standby current draw (’960 Patent, col. 3:26-33). The selection of which sections to refresh is governed by control signals generated in response to a programmable address signal (’960 Patent, col. 8:56-60).
• Technical Importance: This selective refresh approach directly addresses the demand for lower power consumption in electronic devices, which can translate to longer standby times and improved battery life (’960 Patent, col. 2:50-56).

Key Claims at a Glance

The complaint alleges infringement of "one or more claims" without specifying which ones (Compl. ¶11). The broadest independent claims appear to be method claim 1 and apparatus claim 10.

• Independent Claim 1 (Method):
  • controlling background operations (e.g., refresh) in each of a plurality of memory sections in response to one or more control signals;
  • wherein the control signals are generated in response to a programmable address signal, and the background operations can be enabled simultaneously in two or more sections independently of any other section;
  • presenting the control signals and decoded address signals to one or more periphery array circuits of the sections.
• Independent Claim 10 (Apparatus):
  • a memory array comprising a plurality of sections, each having periphery array circuitry to control access to memory cells;
  • a control circuit configured to present control signals and decoded address signals to the periphery array circuitry;
  • wherein the control signals are generated from a programmable address signal and can enable a background operation in two or more sections independently.

The complaint does not explicitly reserve the right to assert other claims, but this is standard practice.

III. The Accused Instrumentality

Product Identification

• The complaint does not identify any accused products or services by name. It refers to "Exemplary Defendant Products" that are purportedly identified in charts within an Exhibit 2 (Compl. ¶¶11, 13). This exhibit was not included with the filed complaint document.

Functionality and Market Context

• The complaint does not provide sufficient detail for analysis of the accused instrumentality's functionality or market context.

IV. Analysis of Infringement Allegations

The complaint alleges infringement by incorporating by reference claim charts from an unprovided "Exhibit 2" (Compl. ¶13). As such, the specific factual basis for the infringement allegations is not contained within the provided document. The analysis below is based on the structure of the patent's independent claims, noting where the complaint lacks corresponding factual allegations.

No probative visual evidence provided in complaint.

'960 Patent Infringement Allegations

• Identified Points of Contention:
  • Evidentiary Question: The complaint provides no factual allegations or evidence to support its claims of infringement. The primary point of contention will be whether the Plaintiff can produce evidence in discovery to show that Defendant’s products, once identified, actually practice each element of the asserted claims.
  • Technical Question: A key technical question will be whether any power-saving modes in the accused products are implemented using the specific architecture of the ’960 Patent—namely, by selectively disabling the "periphery array circuits" of distinct memory "sections"—or if they employ a different, non-infringing power management technique.

V. Key Claim Terms for Construction

• The Term: "periphery array circuits" (Claim 1)

• Context and Importance: This term defines the specific components that are selectively enabled or disabled to save power. The infringement analysis will depend on whether the circuitry within the accused products that is controlled during power-saving modes qualifies as "periphery array circuits" under the patent's definition.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent states these circuits "each comprise one or more circuits from the group consisting of sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" (’960 Patent, col. 8:65-col. 9:1). A party may argue that the phrase "consisting of" introduces a list of examples and that the term should cover any circuitry used to access the memory cells, as described functionally elsewhere (’960 Patent, col. 3:24-26).
  • Evidence for a Narrower Interpretation: A party may argue that the term is limited to the specific set of four circuit types explicitly listed in claim 5 and shown in the detailed embodiment of Figure 5 (e.g., wordline driver 160, equalization circuit 162, sense amplifiers 164, multiplexer 166).

• The Term: "programmable address signal" (Claim 1)

• Context and Importance: This signal is the input that dictates which memory sections are selected for the background operation. Practitioners may focus on this term because its construction will determine what kind of user or system-level control mechanism meets this limitation.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The term is not explicitly defined, which may support an argument for its plain and ordinary meaning: any address signal that can be programmed or set to designate a portion of the memory.
  • Evidence for a Narrower Interpretation: The specification describes a specific implementation where a "refresh block address" (AR1) is loaded into a "refresh address register" (138) to generate the "REF_BLK" signal, which in turn controls the selection (’960 Patent, col. 4:56-67; Fig. 3). A party may argue the term should be limited to this disclosed register-based mechanism or its structural equivalent.

VI. Other Allegations

• Indirect Infringement: The complaint does not plead any facts to support, nor does it include a count for, indirect infringement.
• Willful Infringement: The complaint does not contain a count for willful infringement or allege any facts regarding pre-suit knowledge by the Defendant. The prayer for relief includes a request that the case be declared "exceptional" under 35 U.S.C. § 285, which is the statute for awarding attorney fees, but does not provide a factual basis for such a finding (Compl. ¶E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

• Evidentiary Substantiation: The most immediate question is one of evidentiary sufficiency: can the plaintiff move beyond the complaint's conclusory allegations and unprovided exhibits to produce concrete evidence that specifically identified products from the defendant practice each limitation of the asserted claims?
• Technical Congruence: A central issue will be one of technical alignment: assuming the defendant's products incorporate power-saving memory features, do those features operate according to the specific architecture of the ’960 patent—by selectively deactivating "periphery array circuits" for independent memory "sections"—or do they achieve power reduction through an alternative, non-infringing mechanism?
• Definitional Scope: The case may turn on a question of claim construction, particularly for the term "periphery array circuits." The outcome could hinge on whether the court adopts a broader functional definition or a narrower interpretation limited to the specific circuit types disclosed in the patent's embodiments.