DCT
2:25-cv-00243
Ascale Tech LLC v. Texas Instruments Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Ascale Technologies LLC (Texas)
- Defendant: Texas Instruments, Inc. (Delaware)
- Plaintiff’s Counsel: Fabricant LLP
- Case Identification: 2:25-cv-00243, E.D. Tex., 02/27/2025
- Venue Allegations: Venue is predicated on Defendant having a regular and established place of business in the district, including an operational commercial manufacturing facility and a new chip manufacturing facility under construction.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor products, including multi-core processors and power management integrated circuits, infringe patents related to thread scheduling, power management, and processor performance optimization.
- Technical Context: The technologies at issue concern methods for improving performance and power efficiency in complex systems-on-chip, which are foundational components in markets ranging from automotive to industrial applications.
- Key Procedural History: The complaint asserts that Defendant had knowledge of the patents-in-suit due to its position as a direct competitor to Freescale Semiconductor, the original assignee of the patents. This assertion forms the basis for the willfulness allegations.
Case Timeline
| Date | Event |
|---|---|
| 2006-02-13 | U.S. Patent No. 7,490,266 Priority Date |
| 2008-01-22 | U.S. Patent No. 8,739,165 Priority Date |
| 2009-02-10 | U.S. Patent No. 7,490,266 Issues |
| 2012-09-28 | U.S. Patent No. 8,984,254 Priority Date |
| 2014-05-27 | U.S. Patent No. 8,739,165 Issues |
| 2015-03-17 | U.S. Patent No. 8,984,254 Issues |
| 2025-02-27 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,739,165 - "Shared Resource Based Thread Scheduling With Affinity and/or Selectable Criteria"
- Issued: May 27, 2014
The Invention Explained
- Problem Addressed: The patent’s background section notes that in multi-core processing systems, the method by which software tasks (threads) are assigned to different processor cores can have a significant impact on system performance and power consumption (’165 Patent, col. 1:10-18).
- The Patented Solution: The invention describes a method for scheduling threads that considers whether the goal is to minimize power or maximize performance. The system also evaluates "thread affinity," which is a measure of how suitable a core is for a given thread, based in part on whether data for that thread is already present in the core's local cache. (’165 Patent, Abstract; col. 2:10-26). The flowchart in Figure 1 illustrates decision logic for selecting a core based on these competing criteria (’165 Patent, Fig. 1).
- Technical Importance: This approach allows a processor to make dynamic, context-aware scheduling decisions, which is critical for balancing performance and power efficiency in modern computing devices (’165 Patent, col. 3:36-49).
Key Claims at a Glance
- The complaint asserts independent claim 10 (Compl. ¶22).
- Essential elements of independent claim 10 include:
- An apparatus with a plurality of processors and control circuitry.
- Core availability circuitry to determine if a core is available.
- Core affinity circuitry to determine if a core has an affinity for a thread, where this determination comprises "counting a number of writes by one or more other threads to a cache associated with the core since the thread was last executed by the core."
- Monitoring circuitry for monitoring characteristics of the apparatus.
- Select circuitry for selecting a processor to execute the thread based on the affinity and the monitored characteristics.
- The complaint seeks relief based on infringement of "one or more claims," which may suggest an intent to assert dependent claims later (Compl. p. 28, ¶a).
U.S. Patent No. 7,490,266 - "Integrated Circuit and Processing System with Improved Power Source Monitoring and Methods For Use Therewith"
- Issued: Feb. 10, 2009
The Invention Explained
- Problem Addressed: The patent addresses the risk of electronic devices malfunctioning, crashing, or "hanging-up" due to power source interruptions, such as a low battery condition or disconnection of an external supply (’266 Patent, col. 1:26-34).
- The Patented Solution: The patent describes a processing system that includes a processing module and a distinct power monitor circuit. This dedicated monitor circuit observes the power source for error conditions (e.g., low voltage). Upon detecting an error, the monitor circuit is configured to initiate an organized power-down of the processing module and power source to prevent a system crash. (’266 Patent, Abstract; col. 2:15-26). Figure 4 illustrates this architecture, showing the "Power monitor circuit 120" as separate from, but coupled to, the "Processing module 100" and "Power source 110" (’266 Patent, Fig. 4).
- Technical Importance: This design provides a robust, hardware-based failsafe for managing power faults, enhancing the reliability of integrated circuits, particularly in battery-powered devices where power stability is not guaranteed (’266 Patent, col. 2:30-40).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶36).
- Essential elements of independent claim 1 include:
- A processing system with a DC-DC converter configured to generate a supply voltage when coupled to a battery.
- A memory module to store operational instructions.
- A processing module, powered by the DC-DC converter, to execute the instructions.
- A power monitor circuit that is "distinct from and in communication with the processing module."
- The power monitor circuit is configured to monitor the DC-DC converter and "to power down the DC-DC converter and the processing module" when a first error condition is detected.
U.S. Patent No. 8,984,254 - "Techniques for Utilizing Translation Lookaside Buffer Entry Numbers to Improve Processor Performance"
- Issued: March 17, 2015 (Compl. ¶10)
Technology Synopsis
- The patent discloses a method to accelerate processor operations by using a Translation Lookaside Buffer (TLB) entry number (composed of a TLB "way" and "index") for certain high-speed address comparisons, rather than using the full, and much longer, physical address. This technique is intended to reduce the latency and power consumption associated with tasks like store-to-load data forwarding by comparing fewer bits to determine if two virtual addresses point to the same physical memory location (’254 Patent, Abstract; col. 4:10-22).
Asserted Claims & Accused Features
- Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶50).
- Accused Features: The complaint accuses ARM-based processors, such as the TDA4VEN Jacinto, that use a Memory Management Unit (MMU) and TLBs for virtual-to-physical address translation. The infringement theory focuses on the processor's handling of memory aliasing and TLB invalidation instructions, alleging that these functions inherently involve determining if two different virtual addresses map to the same TLB way and index, thereby meeting the claim limitations (Compl. ¶¶ 52-54).
III. The Accused Instrumentality
Product Identification
- The complaint names broad categories of semiconductor products, with specific examples identified for each patent: the TDA4VM Processors for the ’165 Patent and the AM62x Sitara Processors (used with a PMIC like the TPS6521905) for the ’266 Patent (Compl. ¶¶ 18, 21, 35).
Functionality and Market Context
- TDA4VM Processors (’165 Patent): These are identified as multi-core processors featuring a heterogeneous mix of cores, including Arm Cortex-A72 and C7x DSPs (Compl. ¶23, p. 7). The complaint alleges they run operating systems (e.g., Linux, QNX, RTOS) and frameworks (e.g., TIOVX) that support advanced workload scheduling, including task priority and core affinity, for use in demanding applications like automotive systems (Compl. ¶24).
- AM62x Sitara Processors (’266 Patent): These are described as Systems-on-Chip (SoCs) that operate in conjunction with an external Power Management Integrated Circuit (PMIC) (Compl. ¶¶ 35, 41). The complaint alleges the AM62x processor receives power from the PMIC’s DC-DC converters, which can be supplied by a battery (Compl. ¶38). The PMIC is alleged to monitor the power rails for errors, such as undervoltage, and notify the main processor of faults (Compl. ¶41, p. 20). The complaint includes an "Example Power Map" diagram from a TI datasheet showing the PMIC supplying various voltages to the processor (Compl. p. 19).
IV. Analysis of Infringement Allegations
’165 Patent Infringement Allegations
| Claim Element (from Independent Claim 10) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an apparatus, comprising: a plurality of processors; and control circuitry, coupled to the plurality of processors | The accused TDA4VM Processors contain a plurality of processor cores (e.g., Arm Cortex-A72, C7x DSP) and control circuitry, such as a controller running an operating system (Linux, QNX, RTOS) that manages the cores. | ¶¶23-24 | col. 5:39-44 |
| said control circuitry comprising: core availability circuitry for determining if a core is available to execute a thread | The TDA4VM's controller and kernel architecture allegedly determine core availability using features like a Multiprocessor Affinity Register (MPIDR), interrupt controller, and power management circuitry. | ¶25 | col. 5:45-47 |
| core affinity circuitry for determining if the core has an affinity for the thread, wherein said determining if the core has an affinity for the thread comprises counting a number of writes by one or more other threads to a cache associated with the core since the thread was last executed by the core | The complaint alleges on information and belief that the ARM architecture in the TDA4VM monitors events like cache access and write-backs to count writes by other threads. This is allegedly used to interpret thread affinity and is supported by documentation showing "core_affinity" as a scheduling parameter. A screenshot from an ARM manual describes a hierarchical "Affinity routing and assignment" scheme (Compl. p. 13). | ¶[p.11, ¶1] | col. 2:56-64 |
| monitoring circuitry for monitoring one or more characteristics of the apparatus | The TDA4VM's controller allegedly includes a power monitoring unit and other circuitry that measures characteristics such as task priority, power consumption, temperature, and workload demand. | ¶26 | col. 5:50-52 |
| and select circuitry for selecting one or more of the plurality of processors to execute the thread based on the affinity for the thread and the one or more characteristics of the apparatus. | The TDA4VM controller is alleged to select a processor core for a task based on an affinity score and other characteristics like task priority and power consumption. | ¶27 | col. 5:52-56 |
Identified Points of Contention (’165 Patent)
- Evidentiary Question: The complaint's allegation for the "counting a number of writes" limitation rests on "information and belief." A central question will be what evidence, if any, demonstrates that the accused TDA4VM processors perform this specific counting method to determine affinity, as opposed to using a more general or different mechanism (e.g., a time-based heuristic) that may fall outside the literal scope of the claim.
- Scope Question: Does the high-level concept of "core affinity" supported by the accused TIOVX framework necessarily implement the specific "counting a number of writes" method recited in claim 10?
’266 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a direct current to direct current (DC-DC) converter configured to generate a supply voltage when coupled to a battery | The accused AM62x Sitara processor is used with a PMIC (e.g., TPS6521905) that contains synchronous step-down DC-DC converters and can be supplied by a single-cell Li-Ion battery. | ¶38 | col. 12:65-67 |
| a memory module configured to store a plurality of operational instructions | The AM62x Sitara processor includes on-chip RAM, DDR memory, EEPROM, and flash memory for storing instructions. | ¶39 | col. 7:1-3 |
| a processing module, operatively coupled to the memory module, that is configured to execute the plurality of operational instructions, the processing module receiving power from the DC-DC converter | The AM62x Sitara processor contains multiple cores that execute instructions and receive power from the PMIC's DC-DC converter. The complaint provides an "Example Power Map" diagram showing BUCK converters from the PMIC supplying the processor's "VDD_CORE" pin (Compl. p. 19). | ¶40 | col. 7:4-9 |
| and a power monitor circuit, operatively coupled to the DC-DC converter, that is distinct from and in communication with the processing module and that is configured to... power down the DC-DC converter and the processing module when a first error condition is detected... | The AM62x Sitara system includes a PMIC or PMU alleged to be the distinct power monitor circuit. This circuit allegedly monitors the DC-DC converters for undervoltage errors and is configured to "manage the DC-DC converter and to power down the DC-DC converter and the processing module" when an error is detected. The complaint cites documentation stating a fault-pin ("nINT") "notifies the SoC about faults." | ¶41 | col. 7:10-18 |
Identified Points of Contention (’266 Patent)
- Scope Question: Does a PMIC that "notifies the SoC about faults" via an interrupt pin (Compl. p. 20) meet the claim limitation of a circuit that is itself "configured to... power down the DC-DC converter and the processing module"? The dispute may turn on whether signaling a fault is legally equivalent to directly executing the power-down action, as the patent's abstract describes the monitor circuit "powers down the power source" (’266 Patent, Abstract).
- Technical Question: What is the specific sequence of events in the accused system when an undervoltage condition is detected? Does the PMIC autonomously cut power, or does it merely send a signal that the main processor interprets and acts upon, potentially giving the processor final control over the shutdown sequence?
V. Key Claim Terms for Construction
’165 Patent
- The Term: "counting a number of writes by one or more other threads to a cache"
- Context and Importance: This term defines the specific mechanism for calculating thread affinity. Infringement of claim 10 hinges on whether the accused products implement this exact method. Practitioners may focus on this term because the complaint alleges it on "information and belief," suggesting it may be a point of factual weakness that will be explored in discovery.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification discusses various ways to determine affinity, including tracking the cache replacement algorithm or the duration of execution of other threads, which could suggest that "counting writes" is an exemplary, not exclusive, way of measuring cache state changes (’165 Patent, col. 2:45-67).
- Evidence for a Narrower Interpretation: The claim language is highly specific. The specification provides a direct antecedent for this language, stating, "the circuitry may count the number of writes by other threads to a cache last used by a particular thread" (’165 Patent, col. 2:56-59). This may support an argument that the claim is limited to a literal counting mechanism.
’266 Patent
- The Term: "power monitor circuit... configured to... power down the DC-DC converter and the processing module"
- Context and Importance: This term is critical because it defines the required capability and action of the monitor circuit. The infringement analysis will turn on whether the accused PMIC's function of signaling a fault to the main processor constitutes being "configured to power down" the system.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent’s Figure 4 shows the power monitor circuit 120 issuing a "PS power down signal 109" to the power source and a "PM power down signal 122" to the processing module. This could support an argument that the circuit is "configured to power down" the system by initiating the controlling signals that cause the shutdown, even if other components execute the final steps (’266 Patent, Fig. 4).
- Evidence for a Narrower Interpretation: The abstract states the "power monitor circuit... powers down the power source" (’266 Patent, Abstract). Further, claim 1 requires the circuit to be distinct from the processing module. This could support a reading that the monitor circuit must act autonomously to cut power, not merely provide an input to the very processing module it is supposed to be independently monitoring.
VI. Other Allegations
Indirect Infringement
- For all three patents, the complaint alleges induced infringement based on Defendant providing the accused products with "instructions, documentation, ... SDKs, marketing, product manuals, advertisements, and online documentation" that allegedly instruct customers and end-users on how to use the products in an infringing manner (e.g., Compl. ¶¶ 28, 42, 55). The complaint also alleges contributory infringement, stating the accused components are material, not staple articles of commerce, and are known by Defendant to be especially adapted for infringement (e.g., Compl. ¶¶ 29, 43, 56).
Willful Infringement
- The complaint alleges willful infringement for all patents-in-suit. The allegations are based on purported pre-suit knowledge, stemming from Defendant's status as a "direct competitor to Freescale," the original patent assignee, which allegedly led Defendant to monitor or be aware of the patents. In the alternative, the complaint alleges willful blindness based on a purported policy of not reviewing the patents of others (Compl. ¶¶ 17, 30, 44, 57).
VII. Analyst’s Conclusion: Key Questions for the Case
- A key evidentiary question will be one of technical proof: can Plaintiff produce evidence that TI's affinity scheduling in its TDA4VM processor performs the specific method of "counting a number of writes... to a cache" as recited in the ’165 Patent, or will discovery show that the accused feature is a more generalized, non-infringing mechanism?
- A core issue will be one of functional scope: does the accused PMIC in the AM62x Sitara system, which the complaint indicates "notifies the SoC about faults," perform the function of a "power monitor circuit... configured to... power down" the system as required by the ’266 Patent, or is there a legally significant distinction between signaling a fault and autonomously executing a power-down sequence?
- A central dispute will likely concern claim construction: the viability of the infringement theories for both the ’165 and ’266 patents will depend heavily on whether the court adopts a broader, functional interpretation of key claim terms or a narrower, more literal one based on specific embodiments described in the patents.