Edgecomm LLC v. Advantech Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: EdgeComm LLC (NM)
  • Defendant: Advantech Co., Ltd. (Taiwan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:25-cv-00537, E.D. Tex., 05/16/2025
• Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation and has committed acts of patent infringement in the district.
• Core Dispute: Plaintiff alleges that certain of Defendant's products infringe a patent related to an architecture for accessing memory units using a packet-based serial interface.
• Technical Context: The technology addresses the "memory wall" problem, where the speed of communication between a computer's processor and its memory creates a performance bottleneck.
• Key Procedural History: Plaintiff EdgeComm LLC is the assignee of the patent-in-suit. The complaint does not mention any prior litigation, inter partes review proceedings, or licensing history.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,234,483 - Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface

• Issued: July 31, 2012.

The Invention Explained

• Problem Addressed: The patent’s background section identifies the performance gap between fast processors and slower memory access, often called the “memory wall” or “memory gap” (U.S. Patent No. 8,234,483, col. 3:15-24). This bottleneck is exacerbated by traditional parallel bus architectures, which are difficult to scale to higher speeds and consume significant circuit board space (’483 Patent, col. 2:59-67).
• The Patented Solution: The invention replaces the conventional parallel bus between a processor and memory with a high-speed, packet-switched serial interface, akin to protocols like Ethernet used for network I/O (’483 Patent, Abstract). The core of the solution is a “packet processor” that is integrated onto the same semiconductor die package as the memory device itself (’483 Patent, col. 12:46-50). This processor converts standard memory commands (e.g., read, write) into data packets for transmission over the serial interface and decapsulates incoming packets back into memory commands (’483 Patent, col. 5:25-35).
• Technical Importance: By using a serial, packet-based protocol for memory access, the invention proposes a more scalable method to overcome the bandwidth limitations of parallel buses, potentially allowing memory systems to keep pace with increasing processor speeds (’483 Patent, col. 4:48-57).

Key Claims at a Glance

• The complaint asserts "Exemplary '483 Patent Claims" without identifying specific claims (Compl. ¶11). Independent claim 1 is representative of the apparatus disclosed.
• Independent Claim 1 of the '483 Patent recites the following essential elements:
  • An apparatus comprising at least one memory device.
  • At least one packet processor "uniquely associated with" each memory device.
  • The packet processor is adapted to provide read/write access to the memory device via a "high-speed packet switched serial interface."
  • This is accomplished by "decapsulating" information from an incoming packet and "encapsulating" data into an outgoing packet.
  • A key structural limitation is that the memory device and the packet processor are "co-located on a semiconductor die package" which has an external port for the serial interface.

III. The Accused Instrumentality

Product Identification

• The complaint refers to "Exemplary Defendant Products" (Compl. ¶11).

Functionality and Market Context

• The complaint alleges that infringement is detailed in charts in "Exhibit 2" (Compl. ¶16, ¶17). However, Exhibit 2 was not provided with the complaint. Therefore, the complaint does not provide sufficient detail for analysis of the specific accused products or their functionality.

IV. Analysis of Infringement Allegations

The complaint references but does not include the claim charts from Exhibit 2 that allegedly detail the infringement (Compl. ¶17). The complaint’s narrative alleges that the "Exemplary Defendant Products practice the technology claimed by the '483 Patent" and "satisfy all elements of the Exemplary '483 Patent Claims" (Compl. ¶16). Without the specific product details or claim charts, a tabular analysis is not possible.

No probative visual evidence provided in complaint.

Identified Points of Contention

Based on the patent and the general nature of the allegations, the infringement analysis may raise several technical and legal questions:

• Scope Questions: A central question will be whether a standard memory controller or a system-on-a-chip (SoC) component in the accused products can be characterized as a "packet processor" as the term is used in the '483 Patent. The dispute may turn on whether the accused component performs the specific claimed functions of encapsulating and decapsulating memory commands into a "predefined serial protocol format."
• Technical Questions: A key factual question is whether the accused products meet the structural limitation that the memory device and the "packet processor" are "co-located on a semiconductor die package" ('483 Patent, col. 12:46-50). Evidence will be needed to determine if the relevant processing logic is physically integrated onto the same chip package as the memory cells, or if it resides on a separate processor or controller chip.

V. Key Claim Terms for Construction

"packet processor"

• Context and Importance: This term is foundational to the invention. The outcome of the case may depend on whether the functionality of a component within the accused products falls within the scope of this term. Practitioners may focus on this term because it is not a standard industry term and its meaning is defined by the patent's specification.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the component's function broadly as a "protocol processor" that "encapsulates the memory address and control information...as an Ethernet packet" ('483 Patent, Abstract). It can also be implemented as an "on the fly programmable bit stream protocol processor" ('483 Patent, col. 5:18-21), suggesting functional flexibility rather than a fixed hardware structure.
  • Evidence for a Narrower Interpretation: The patent provides detailed block diagrams (e.g., FIG. 3A) showing a "packet processor" with specific sub-components like an "Encapsulation Engine," "Decapsulation Engine," and "Egress/Ingress Traffic Manager" ('483 Patent, col. 8:41-55). A party could argue the term should be limited to an architecture containing these specific elements.

"co-located on a semiconductor die package"

• Context and Importance: This structural limitation is a critical point of distinction for the invention. Infringement requires this specific physical integration. Whether an accused product, which might have memory and controller functions on the same circuit board but on different chips, meets this limitation will be a core issue.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The complaint does not provide sufficient detail for analysis of this element.
  • Evidence for a Narrower Interpretation: The claim language itself is specific. The patent consistently illustrates this concept, for example in FIG. 2C, which depicts a single "Memory Chip" (70) containing both memory and a "Protocol Converter" ('483 Patent, FIG. 2C). FIG. 5B likewise shows a "Mmeory Chip Package" (70) containing both memory devices and a "Parallel Bus to Serial Interface Converter" ('483 Patent, FIG. 5B). This evidence suggests the term requires physical integration on a single packaged chip, not merely on a common motherboard.

VI. Other Allegations

Indirect Infringement

• The complaint alleges induced infringement, stating that Defendant distributes "product literature and website materials inducing end users and others to use its products in the customary and intended manner that infringes" (Compl. ¶14). The allegation of knowledge for inducement is based on knowledge "at least since being served by this Complaint" (Compl. ¶15).

Willful Infringement

• The willfulness allegation appears to be based on post-suit conduct. The complaint alleges that service of the complaint and its attached charts "constitutes actual knowledge of infringement" and that Defendant's continued infringing activities despite this knowledge are willful (Compl. ¶¶13-14). Plaintiff also requests that the case be declared "exceptional" under 35 U.S.C. § 285 (Compl. Prayer for Relief ¶E(i)).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A core issue will be one of definitional scope: can the term "packet processor," as described and claimed in the '483 Patent, be construed to read on the functionality of a memory controller or similar component in a modern computing architecture, or is it limited to the specific embodiments shown in the patent's figures?
2. The case will likely involve a crucial structural and evidentiary question: what evidence will show whether the accused products physically integrate memory and the accused "packet processor" functionality onto a single "semiconductor die package" as required by the claims, versus implementing them as discrete components on a larger circuit board?
3. A central question of proof will be whether Plaintiff can demonstrate that the accused products, in operation, actually perform the claimed functions of "encapsulating" and "decapsulating" memory commands into and from packets conforming to a "predefined serial protocol format."