Edgecomm LLC v. Silicom Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: EdgeComm LLC (New Mexico)
  • Defendant: Silicom Ltd. (Israel)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 2:25-cv-00539, E.D. Tex., 05/18/2025
• Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation and has committed acts of patent infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant’s products infringe a patent related to the architecture for communication between computer processors and memory units.
• Technical Context: The technology concerns methods for overcoming data transfer bottlenecks between central processing units and system memory, a critical factor in high-performance computing system design.
• Key Procedural History: The complaint does not reference any prior litigation, inter partes review (IPR) proceedings, or licensing history related to the patent-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,234,483 - "Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface," issued July 31, 2012

The Invention Explained

• Problem Addressed: The patent describes a "divergence between processor speeds and memory access speeds," often called the "memory wall problem" or the "Von Neuman Bottleneck." (’483 Patent, col. 3:15-20, col. 2:18). Traditional parallel bus architectures connecting processors to memory are described as prone to "clock skew" at high speeds and take up considerable circuit board space, limiting performance improvements. (’483 Patent, col. 2:58-68).
• The Patented Solution: The invention proposes replacing the traditional parallel bus with a high-speed, packet-switched serial interface, such as Ethernet, for processor-memory communication. (’483 Patent, Abstract). The core of the solution is a "packet processor" integrated with a memory device on a single semiconductor die. This processor is responsible for receiving memory access requests (e.g., read/write commands) from an external device, decapsulating them from a serial packet format, and encapsulating the resulting data into a new packet for transmission back to the external device. (’483 Patent, col. 12:35-53; Fig. 3B).
• Technical Importance: This architecture aims to negate the physical and speed limitations of parallel buses, allowing processor-memory communication speeds to scale with advancements in serial I/O technologies like multi-gigabit Ethernet. (’483 Patent, col. 2:50-55).

Key Claims at a Glance

• The complaint does not identify specific claims but refers to "Exemplary '483 Patent Claims" in a referenced exhibit not attached to the complaint. (Compl. ¶11, ¶16). Independent claim 1 is representative of the invention’s core concept.
• Independent Claim 1:
  • An apparatus implementing a computing and communication chip architecture for integrated circuitry, comprising:
  • at least one memory device; and
  • at least one packet processor uniquely associated with each of the at least one memory device, and
  • the at least one packet processor adapted to provide an external device read and write access to the at least one memory device via at least one high-speed packet switched serial interface, by decapsulating address, data and control information, contained in a packet conforming to a predefined serial protocol format received from the external device, and
  • encapsulating data including the decapsulated address and control information into another packet conforming to the said serial protocol format for transmission to the said external device, in response to the received packet, and
  • wherein the at least one memory device and the at least one packet processor are co-located on a semiconductor die package having at least one external port over which the high-speed packet switched serial interface is accessible...
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

• The complaint does not identify any specific accused products by name. It refers generally to "Exemplary Defendant Products" that are purportedly identified in an external document, Exhibit 2, which was not filed with the complaint. (Compl. ¶11, ¶16).

Functionality and Market Context

• The complaint alleges that Defendant makes, uses, sells, and imports products that "practice the technology claimed by the '483 Patent." (Compl. ¶11, ¶16). No specific technical details regarding the functionality or market position of any accused product are provided in the complaint itself.

IV. Analysis of Infringement Allegations

The complaint provides no narrative infringement theory in its main body. Instead, it states that Exhibit 2, which was not provided, "includes charts comparing the Exemplary '483 Patent Claims to the Exemplary Defendant Products" and that these charts demonstrate that the products "satisfy all elements" of the asserted claims. (Compl. ¶16, ¶17). Without this exhibit, a detailed analysis of the infringement allegations is not possible based on the provided documents.

No probative visual evidence provided in complaint.

V. Key Claim Terms for Construction

"packet processor"

• Context and Importance: This term is central to the invention, as it describes the active component that enables the use of a serial packet protocol for memory access. The definition will be critical to determining if an accused device performs the claimed functions. Practitioners may focus on whether this term requires a dedicated, programmable processor, as described in some embodiments, or if it could read on more generic I/O controllers.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claims define the term functionally as a component that "decapsulat[es]" and "encapsulat[es]" information for access to a memory device via a serial interface. (’483 Patent, col. 12:35-49). This functional language may support an interpretation covering any component that performs these steps, regardless of its specific implementation.
  • Evidence for a Narrower Interpretation: The specification describes the packet processor in some embodiments as an "on the fly programmable bit stream processor" or a "Bitstream processor," which is a "programmable integrated packet processor, security engine and traffic manager." (’483 Patent, col. 8:61-66). This could support a narrower construction requiring programmability or specific traffic management features not present in all serial interface controllers.

"co-located on a semiconductor die package"

• Context and Importance: This limitation defines the physical relationship between the memory device and the "packet processor". Its construction will determine the required level of physical integration for infringement. The dispute will likely center on whether "co-located on a semiconductor die package" means integrated onto the very same piece of silicon (a system-on-chip design) or could encompass separate chips mounted on a single substrate or package.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term "package" could be argued to be broader than "die," potentially covering multi-chip modules where separate dies are housed within a single physical package.
  • Evidence for a Narrower Interpretation: The patent repeatedly emphasizes integration onto a single "chip" or "die." For example, the abstract refers to a "protocol processor integrated as part of the chip," and the summary mentions a "packet processor co-located with at least one processor core within the chip package." (’483 Patent, Abstract; col. 5:4-6). Figure 2C and its description show the packet processor located on the processor "die in an integrated configuration." (’483 Patent, col. 8:23-24). This consistent emphasis on tight integration may support a narrower construction.

VI. Other Allegations

• Indirect Infringement: The complaint alleges that Defendant induces infringement by distributing "product literature and website materials" that instruct end users on how to use the accused products in a manner that infringes. (Compl. ¶14, ¶15).
• Willful Infringement: The complaint does not use the term "willful." It alleges that the service of the complaint itself provides Defendant with "Actual Knowledge of Infringement." (Compl. ¶13). This allegation appears to support a claim only for post-suit, rather than pre-suit, enhanced damages.

VII. Analyst’s Conclusion: Key Questions for the Case

1. Evidentiary Sufficiency: A threshold issue is the complaint's complete reliance on an unfiled exhibit to provide the factual basis for infringement. The case will depend on Plaintiff substantiating its conclusory allegations by identifying the specific accused products and articulating a plausible infringement theory for each element of the asserted claims.
2. Claim Scope and Technical Match: A core technical dispute will likely be one of definitional scope: can the term "packet processor", as defined in the patent, be construed to cover the architecture of the accused products once they are identified? This will turn on whether the accused functionality performs the specific "encapsulating" and "decapsulating" steps required by the claims.
3. Physical Implementation: A key question of claim construction will concern the physical scope of the term "co-located on a semiconductor die package". The resolution of this issue will determine whether infringement requires a system-on-chip (SoC) design or could also be met by systems with discrete memory and controller chips mounted on a common board or multi-chip module.