DCT

2:25-cv-00552

Netlist Inc v. Micron Technology Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-00552, E.D. Tex., 05/19/2025
  • Venue Allegations: Venue is alleged based on Defendants maintaining regular and established places of business in the Eastern District of Texas and committing acts of patent infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s High Bandwidth Memory (HBM) products infringe a patent related to methods for partitioning electrical interconnects within stacked-die memory packages to reduce driver load and power consumption.
  • Technical Context: The lawsuit concerns high-performance memory technologies, such as HBM, which are critical components for data-intensive applications like artificial intelligence, cloud computing, and high-performance computing.
  • Key Procedural History: The complaint highlights a history of litigation between the parties and their competitors, referencing prior jury verdicts where Netlist prevailed against Samsung and Micron on other patents. Plaintiff also preemptively seeks a declaratory judgment that this lawsuit was not brought in bad faith, referencing what it characterizes as "retaliatory suits" filed by Micron in Idaho.

Case Timeline

Date Event
2010-11-03 '087 Patent Priority Date
2025-05-19 Complaint Filing Date
2025-05-20 '087 Patent Issue Date

II. Technology and Patent(s)-in-Suit Analysis

  • Patent Identification: U.S. Patent No. 12,308,087, "Memory Package Having Stacked Array Dies and Reduced Driver Load," issued May 20, 2025.

The Invention Explained

  • Problem Addressed: In memory packages with vertically stacked semiconductor dies, a single driver on a control chip must send signals to all dies in the stack through a shared interconnect. This creates a significant electrical load, requiring large, power-hungry drivers that consume valuable chip space. (’087 Patent, col. 2:26-34).
  • The Patented Solution: The invention partitions the communication pathways. Instead of one interconnect serving all dies, it creates multiple, distinct interconnects. A first interconnect serves a first subset of dies, and a second interconnect serves a second subset. This divides the electrical load, allowing for smaller, more efficient drivers for each pathway, thereby reducing power consumption and saving space. (’087 Patent, Abstract; col. 6:11-26; FIG. 2).
  • Technical Importance: This architectural approach aims to solve a fundamental scaling problem in 3D-stacked memory, enabling higher-density memory modules without prohibitive power and size penalties associated with large drivers. (’087 Patent, col. 3:1-4).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶27).
  • Claim 1 recites a dynamic random access memory (DRAM) package with essential elements including:
    • Stacked DRAM dies comprising at least a first and second plurality of DRAM dies.
    • Terminals for receiving command/address (C/A) signals and data signals.
    • Die interconnects, including through-silicon vias (TSVs), that are partitioned into first and second C/A interconnects and first and second data interconnects.
    • A control die coupled between the terminals and the stacked DRAM dies.
    • A first C/A interconnect in electrical communication with the first plurality of DRAM dies but not the second plurality.
    • A second C/A interconnect in electrical communication with the second plurality of DRAM dies but not the first plurality.
    • A first data interconnect in electrical communication with the first plurality of DRAM dies but not the second plurality.
    • A second data interconnect in electrical communication with the second plurality of DRAM dies but not the first plurality.
    • First and second unidirectional interconnects for conducting signals to and from the control die, respectively.
  • The complaint does not explicitly reserve the right to assert dependent claims but incorporates all preceding paragraphs in its claim for relief. (Compl. ¶26).

III. The Accused Instrumentality

Product Identification

  • The Accused Instrumentality includes, without limitation, Micron HBM3E memory and newer products such as HBM4 and HBM4e. (Compl. ¶24).

Functionality and Market Context

  • The complaint alleges the accused products are high-speed computer memory that relies on vertically-stacked memory dies. (Compl. ¶23). These products are marketed for their high performance and lower power consumption, which are key features for generative AI applications. (Compl. ¶23).
  • The accused HBM products are alleged to be compliant with industry standards promulgated by the Joint Electron Device Engineering Council (JEDEC). (Compl. ¶25).
  • The complaint alleges these products are manufactured as "cubes" of 8-high, 12-high, or 16-high stacked DRAM dies, which communicate with a host processor through TSVs. (Compl. ¶¶ 23, 28). The complaint includes a diagram from a Micron blog post illustrating the stacked nature of its HBM3E product. (Compl. ¶28, p. 12).

IV. Analysis of Infringement Allegations

Claim Chart Summary

The complaint provides a narrative infringement theory for claim 1, which is summarized in the table below.

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
[1a] stacked DRAM dies including at least a first plurality of DRAM dies and a second plurality of DRAM dies... The Accused HBM Products are alleged to include stacks of 8, 12, or 16 DRAM dies, which are necessarily divisible into first and second pluralities. A visual from a Micron blog post depicts the stacked die structure. (Compl. p. 12). ¶28 col. 24:45-48
[1c] die interconnects including C/A interconnects and data interconnects...each of the die interconnects including one or more through silicon vias (TSVs)... The products are alleged to use TSVs for communication, which function as the claimed die interconnects. ¶¶28, 30 col. 24:6-9
[1d] a control die coupled between the terminals and the stacked DRAM dies... The Accused HBM Products are alleged to include a "buffer die" or "logic die" that sits between the external terminals and the stacked DRAM dies, which performs the function of the claimed control die. ¶31 col. 24:11-13
[1e] wherein a first C/A interconnect ... is in electrical communication with corresponding C/A ports on the first plurality of DRAM dies and not in electrical communication with ... the second plurality... The complaint alleges that the Accused HBM Products have C/A interconnects that are partitioned to communicate with a first group of dies but not a second. ¶32 col. 24:20-26
[1g] wherein a first data interconnect ... is in electrical communication with corresponding data ports on the first plurality of DRAM dies and not in electrical communication with ... the second plurality... The complaint alleges a similar partitioned structure for the data interconnects, stating that some TSVs electrically connect to some dies in the stack while bypassing others. ¶33 col. 24:32-38
[1k] ...first unidirectional interconnects configured to conduct signals from one or more DRAM dies ... to the control die... The complaint alleges that the unidirectional differential data strobes RDQS_t/RDQS_c defined in the JEDEC standard for HBM3 function as the claimed "first unidirectional interconnects" for read operations. ¶35 col. 24:61-65
[1l] ...second unidirectional interconnects configured to conduct signals from the control die to one or more DRAM dies... The complaint alleges that the unidirectional differential data strobes WDQS_t/WDQS_c defined in the JEDEC standard for HBM3 function as the claimed "second unidirectional interconnects" for write operations. ¶35 col. 25:1-5

Identified Points of Contention

  • Scope Questions: A central question will be whether Micron's JEDEC-compliant HBM architecture falls within the patent's specific claim definitions. For example, does Micron's "logic die" meet all the functional and structural limitations of the claimed "control die"? Similarly, do the industry-standard RDQS/WDQS strobes meet the specific requirements of the claimed "unidirectional interconnects"?
  • Technical Questions: The infringement case may hinge on the negative limitations (i.e., "not in electrical communication with"). The complaint alleges that in the accused products, "some TSVs appear to only electrically interconnect to some of the dies in the stack, while others may electrically bypass certain groups of dies." (Compl. ¶33). A key factual dispute will be whether this alleged bypassing constitutes the distinct, partitioned interconnect structure required by the claims, or if there is a different technical reality in the accused products' wiring.

V. Key Claim Terms for Construction

  • The Term: "control die"

  • Context and Importance: This term is foundational to the claimed invention. The complaint equates it with the "buffer die" or "logic die" in Micron's HBM products (Compl. ¶31). The definition of "control die" will determine whether the accused logic/buffer die, a standard component in HBM architecture, can be mapped to this claim element.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The patent describes the "control die" in functional terms, stating it is "coupled between the terminals and the stacked DRAM dies" and includes "conduits" to route signals ('087 Patent, col. 24:11-19). This functional language could support a reading on any intermediate die that performs these routing tasks.
    • Evidence for a Narrower Interpretation: The patent also describes specific embodiments where the control die contains particular driver structures and logic configured to respond to signals in specific ways ('087 Patent, col. 6:27-34; FIG. 2). A defendant may argue these more detailed descriptions limit the term to a die with these specific capabilities, potentially distinguishing it from a standard HBM logic die.

  • The Term: "in electrical communication with ... and not in electrical communication with"

  • Context and Importance: This negative limitation is the technical crux of the patent's claimed partitioning scheme. Infringement depends entirely on proving that the accused HBM products employ this specific selective connectivity. Practitioners may focus on this term because it creates a high bar for evidentiary proof regarding the physical wiring of microscopic, vertically-stacked components.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The claim language itself is direct. A plaintiff may argue it should be given its plain and ordinary meaning: one set of dies is connected, and another is not. The specification supports this with diagrams like FIG. 2, which clearly show interconnect 220a connecting to dies 210a/210b but not 210c/210d ('087 Patent, FIG. 2).
    • Evidence for a Narrower Interpretation: A defendant may argue that incidental, parasitic, or non-functional electrical coupling does not negate the "not in electrical communication" requirement. The specification's discussion of TSVs that "pass through" but do not connect to certain dies suggests a complete electrical isolation is intended ('087 Patent, col. 6:5-9). The interpretation may turn on the degree and nature of the required electrical separation.

VI. Other Allegations

  • Indirect Infringement: While the formal count is for direct infringement (Compl. ¶27), the complaint alleges facts that may support an indirect infringement theory. It states Defendants "contributed to placing Accused Instrumentalities into the stream of commerce ... knowing or understanding that such products would be sold and used in the United States." (Compl. ¶10). This allegation of knowledge could form the basis for a later claim of induced infringement.
  • Willful Infringement: The complaint requests a finding of willfulness (Compl. ¶(D) in Prayer for Relief). The factual basis appears to rest on the extensive litigation history between the parties, including a prior jury verdict in May 2024 that found Micron liable for infringing other Netlist patents. (Compl. ¶16). This history may be used to argue that Micron was aware of Netlist's patent portfolio and the risk of infringing its patents, supporting a finding of willfulness for at least post-suit conduct.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the patent's specific claim terms, such as "control die" and "unidirectional interconnects", be construed to read on the standardized components and signaling protocols (e.g., JEDEC-compliant logic dies and RDQS/WDQS strobes) used in the accused HBM products? The outcome of claim construction on these terms may be dispositive.
  • A key evidentiary question will be one of technical proof: can the plaintiff produce sufficient evidence to demonstrate that the physical, three-dimensional wiring of the accused HBM products meets the patent's critical negative limitation—that specific interconnects are electrically connected to one subset of stacked dies while being electrically isolated from another? This will likely devolve into a highly technical dispute between experts.
  • A significant legal question, peripheral to infringement, will be the impact of the parties' litigation history: how will the court handle Netlist's unusual request for a declaratory judgment of good-faith assertion and its allegations of "retaliatory" conduct by Micron? This context may influence case management and potential damages assessments, particularly regarding willfulness.