DCT

2:25-cv-00553

Netlist Inc v. Samsung Electronics Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-00553, E.D. Tex., 05/19/2025
  • Venue Allegations: Plaintiff alleges venue is proper because each Defendant maintains a regular and established place of business in the district at 6625 Excellence Way, Plano, Texas, and has committed acts of infringement in the district. The complaint also notes that Defendants have not contested venue in prior litigation in the E.D. Tex.
  • Core Dispute: Plaintiff alleges that Defendant’s High Bandwidth Memory (HBM) products infringe a patent related to methods for managing signal loads in memory packages with vertically stacked dies.
  • Technical Context: The technology at issue involves high-performance, high-density DRAM used in servers for cloud computing, artificial intelligence (AI), and other data-intensive applications.
  • Key Procedural History: The complaint details a significant litigation history between the parties. A 2015 Joint Development and License Agreement (JDLA) was allegedly terminated by Netlist effective July 15, 2020, a date the complaint states was confirmed by a jury verdict. The complaint also cites multiple prior nine-figure jury verdicts that Netlist secured against Samsung and other memory manufacturers in the Eastern District of Texas for infringement of other patents.

Case Timeline

Date Event
2010-11-03 '087 Patent Priority Date
2015-XX-XX Netlist and Samsung enter Joint Development and License Agreement (JDLA)
2020-07-15 Netlist terminates JDLA with Samsung
2022-03-14 '087 Patent Application Filing Date
2023-04-XX E.D. Tex. jury awards Netlist $303.15M against Samsung
2024-02-XX Samsung launches Accused HBM3e Product
2024-XX-XX E.D. Tex. jury awards Netlist $445M against Micron
2024-11-XX E.D. Tex. jury awards Netlist $118M against Samsung
2025-03-24 C.D. Cal. jury returns verdict for Netlist in JDLA contract dispute
2025-05-19 Complaint Filing Date
2025-05-20 '087 Patent Issue Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,308,087 - Memory Package Having Stacked Array Dies and Reduced Driver Load

  • Patent Identification: U.S. Patent No. 12,308,087, issued May 20, 2025 (’087 Patent). (Compl. ¶16).

The Invention Explained

  • Problem Addressed: In memory packages with vertically stacked semiconductor dies (e.g., 3D DRAM), a single driver on the control die must send signals to all dies in the stack. As the number of dies increases, the electrical load on that driver becomes substantial, requiring a larger, more power-hungry driver, which consumes valuable space on the control die. (’087 Patent, col. 2:25-34).
  • The Patented Solution: The patent describes a way to reduce this driver load by partitioning the stack. Instead of one data interconnect serving all dies, the invention uses multiple, distinct data interconnects, where each interconnect is responsible for communicating with only a specific subset of the dies in the stack. This divides the total load, allowing the use of smaller, more efficient drivers for each partitioned signal path. (’087 Patent, Abstract; col. 6:4-24; Fig. 2).
  • Technical Importance: This load-reduction architecture enables higher-density memory modules by allowing more dies to be stacked vertically without incurring the significant power and area costs associated with the larger drivers that would otherwise be required. (’087 Patent, col. 4:3-11).

Key Claims at a Glance

  • The complaint asserts independent Claim 1. (Compl. ¶27).
  • The essential elements of Claim 1 include:
    • A DRAM package with stacked DRAM dies comprising a "first plurality" and a "second plurality" of dies.
    • Terminals for command/address (C/A) and data signals.
    • Die interconnects (including C/A and data interconnects, utilizing Through-Silicon Vias or TSVs) that are partitioned.
    • A "first C/A interconnect" is in communication with the first plurality of dies but not the second; a "second C/A interconnect" is in communication with the second plurality but not the first.
    • A similar partitioning scheme is claimed for the data interconnects.
    • A control die with conduits coupled to the interconnects and control logic to manage data flow.
    • A series of limitations describing first and second "unidirectional interconnects" for managing read and write signals separately.
  • The complaint does not explicitly reserve the right to assert dependent claims, though this is standard practice.

III. The Accused Instrumentality

Product Identification

  • The complaint names Samsung’s High Bandwidth Memory (HBM) products, including HBM2, HBM2E, HBM3, HBM3E (“Shinebolt”), and newer generations such as HBM4. Products marketed as “Aquabolt,” “Flashbolt,” and “Icebolt” are also identified. (Compl. ¶¶22-23).

Functionality and Market Context

  • The Accused HBM Products are high-speed memory components that use vertically stacked DRAM dies interconnected by Through-Silicon Vias (TSVs). (Compl. ¶25). The complaint alleges these products are compliant with JEDEC industry standards and are optimized for high-performance computing (HPC) and artificial intelligence (AI) applications, noting their use in next-generation technologies. (Compl. ¶¶22, 24). The complaint provides a diagram from Samsung's promotional materials showing the HBM product lineup and their increasing data processing speeds. This diagram, titled "Samsung's HBM Lineup," illustrates the commercial evolution and marketing of the accused technology. (Compl. p. 10).

IV. Analysis of Infringement Allegations

The complaint alleges that the Accused HBM Products, by virtue of their stacked-die architecture, meet the limitations of at least Claim 1 of the ’087 Patent.

’087 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A dynamic random access memory (DRAM) package, comprising: [1a] stacked DRAM dies including at least a first plurality of DRAM dies and a second plurality of DRAM dies... The Accused HBM Products are DRAM packages comprised of vertically stacked DRAM dies (e.g., 8, 12, or 16 dies). The complaint includes a diagram showing 4-high and 8-high stacks. (Compl. p. 12). ¶28 col. 5:6-15
[1b] terminals including command and/or address (C/A) terminals and data terminals, wherein the DRAM package is configured to receive C/A signals...and is further configured to receive or output data signals... The Accused HBM Products include C/A and data terminals and operate according to JEDEC standards for read and write operations in response to C/A signals. ¶29 col. 2:41-45
[1c] die interconnects including C/A interconnects and data interconnects...each of the die interconnects including one or more through silicon vias (TSVs)... The Accused HBM Products use TSVs to create connections between the vertically stacked dies. A marketing image is provided to show TSV technology connecting the layers. (Compl. p. 15). ¶30 col. 5:36-40
[1d] a control die coupled between the terminals and the stacked DRAM dies, the control die including conduits... The Accused HBM Products include a control die (also called a "buffer die" or "logic die") at the base of the stack that is coupled to the stacked DRAM dies. ¶31 col. 6:26-34
[1e] wherein a first C/A interconnect...is in electrical communication with corresponding C/A ports on the first plurality of DRAM dies and not in electrical communication with any C/A port on any of the second plurality of DRAM dies; The complaint makes a conclusory allegation that the Accused HBM Products have C/A interconnects in this claimed partitioned configuration. ¶32 col. 6:4-16
[1g] wherein a first data interconnect...is in electrically communication with corresponding data ports on the first plurality of DRAM dies and not in electrical communication with any data port on any of the second plurality of DRAM dies... The complaint alleges the Accused HBM Products have data interconnects in this claimed partitioned configuration, where some TSVs bypass certain groups of dies. ¶33 col. 6:4-16
[1k] & [1l] wherein the die interconnects further include first unidirectional interconnects...and second unidirectional interconnects... The Accused HBM Products allegedly use unidirectional interconnects, such as those for differential data strobes (RDQS_t/RDQS_c and WDQS_t/WDQS_c) defined by the JEDEC standard. ¶35 col. 23:56-24:14
[1j] wherein the control die further includes control logic...wherein the one or more C/A signals do not include any chip select signal; The control logic allegedly operates in response to C/A signals that do not include a chip select signal, as shown in the JEDEC Command Truth Table. ¶34 col. 24:56-62

Identified Points of Contention

  • Scope Questions: A primary question will be whether the specific interconnect partitioning scheme required by the claims (e.g., a "first plurality" of dies served by one interconnect and a "second plurality" served by another, distinct interconnect) is actually present in Samsung's JEDEC-compliant products. The defense may argue that the claims describe a proprietary architecture, while the accused products use a more conventional, standardized bus structure that communicates with dies differently. The interpretation of what constitutes "not in electrical communication" will be crucial.
  • Technical Questions: The infringement theory relies heavily on mapping elements of the JEDEC HBM standard to claim limitations. A key technical question is whether the functional behavior described in the standard (e.g., unidirectional strobes like RDQS/WDQS) is coextensive with the structural requirements of the patent's claims (e.g., "unidirectional interconnects"). The complaint provides a high-level block diagram from the JEDEC standard (Compl. p. 17), but the actual physical implementation within the accused products will be a central point of discovery and dispute.

V. Key Claim Terms for Construction

The Term: "a first plurality of DRAM dies" and "a second plurality of DRAM dies"

  • Context and Importance: The invention's core concept of load reduction is achieved by partitioning the die stack into these distinct "pluralities," each served by separate interconnects. The definition of these terms—specifically whether the pluralities must be mutually exclusive—is fundamental to the scope of the claim.
  • Intrinsic Evidence for a Broader Interpretation: The specification describes selecting a "first subset of array dies and a second subset of array dies" without explicitly requiring them to be disjoint. (’087 Patent, col. 16:40-54). Plaintiff may argue that any two non-identical groupings of dies satisfy the limitation.
  • Intrinsic Evidence for a Narrower Interpretation: The figures and the description of the invention's purpose—to partition and reduce load—suggest the pluralities are intended to be separate groups. Figure 2, for instance, shows die interconnect 220a serving dies 210a-b, while interconnect 220b serves dies 210c-d, implying a clear partition. (’087 Patent, Fig. 2; col. 6:4-24).

The Term: "not in electrical communication with"

  • Context and Importance: This negative limitation is used repeatedly in Claim 1 (e.g., 1e, 1f, 1g) to define the required isolation between the signal paths for the different pluralities of dies. Its construction will be dispositive for infringement.
  • Intrinsic Evidence for a Broader Interpretation (supporting infringement): Plaintiff will likely argue this means no operative or functional connection for the signal at issue. The specification describes a die interconnect passing through an array die "without being in electrical communication with a data port from at least one array die," suggesting that physical proximity or passage through a via without a functional tap does not constitute "electrical communication." (’087 Patent, col. 6:4-9).
  • Intrinsic Evidence for a Narrower Interpretation (against infringement): Defendant may argue for a more literal, physical definition. The patent specification contemplates TSVs that "do not enable electrical communication between the die interconnect...and data ports" of certain dies, which could be interpreted as requiring specific insulating structures. (’087 Patent, col. 8:25-31).

VI. Other Allegations

Willful Infringement

  • The complaint alleges that Samsung’s infringement is willful. (Compl. ¶D in Prayer for Relief). This allegation is based on the extensive, long-running business and litigation history between the parties, including the 2015 JDLA that provided Samsung access to Netlist’s patent portfolio, the subsequent termination of that license in 2020, and multiple prior jury verdicts finding Samsung liable for infringing other Netlist memory patents. (Compl. ¶¶12, 19-21).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of evidentiary proof: beyond high-level marketing materials and general industry standards, what specific evidence can Netlist provide from the accused products themselves to show that Samsung's HBM architecture implements the precise, proprietary partitioning of signal interconnects as recited in the detailed limitations of Claim 1?
  • A key legal question will be one of claim scope vs. industry standard: will the court construe the claims, particularly the negative limitation "not in electrical communication," narrowly to a specific physical layout, or broadly enough to read on functional signal isolation within a standard-compliant JEDEC HBM product? The outcome of claim construction will likely determine whether the patent covers a specific implementation or a more fundamental aspect of stacked-die memory design.
  • A final question will concern the impact of the prior relationship: while the complaint asserts the JDLA license was terminated, the complex history between the parties may open the door for Samsung to raise defenses related to patent exhaustion or implied license rights for products designed or sold during the period the license was operative, potentially limiting the scope of any infringement finding.