DCT

2:25-cv-00557

Netlist Inc v. Samsung Electronics Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-00557, E.D. Tex., 07/08/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendants commit acts of infringement in the district and maintain regular and established places of business there.
  • Core Dispute: Plaintiff alleges that Defendant’s High Bandwidth Memory (HBM) and DDR5 memory modules infringe patents related to stacked memory die architecture and memory module circuits for improving signal integrity.
  • Technical Context: The technology at issue involves high-performance computer memory, a critical component in data-intensive applications such as artificial intelligence, cloud computing, and high-performance servers.
  • Key Procedural History: The complaint references prior patent litigation between the parties, including a May 2024 jury verdict in the Eastern District of Texas where Netlist was awarded $445 million against Micron for infringement of other patents. It also notes that Micron has filed retaliatory suits in Idaho against Netlist.

Case Timeline

Date Event
2008-04-14 ’731 Patent Priority Date
2010-11-03 ’087 Patent Priority Date
2018-07-17 ’731 Patent Issue Date
2021-04-28 Alleged date of Micron's actual knowledge of ’731 Patent
2025-05-20 ’087 Patent Issue Date
2025-07-08 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,308,087 - “Memory Package Having Stacked Array Dies and Reduced Driver Load”

The Invention Explained

  • Problem Addressed: The complaint does not specify a problem addressed by the patent. However, the technical field generally recognizes that increasing memory density by vertically stacking semiconductor dies presents challenges in efficiently routing signals, managing electrical load on drivers, and isolating different groups of dies within the stack.
  • The Patented Solution: The invention describes a memory package architecture where stacked DRAM dies are managed by a separate "control die." This control die routes signals between external terminals and specific pluralities of the stacked DRAM dies using a complex system of interconnects, including through-silicon vias (TSVs) that pass through the dies and distinct unidirectional interconnects for read and write operations (’087 Patent, Abstract; col. 2:8-13; Compl. ¶24). This architecture aims to partition the signal paths to reduce the electrical load on the drivers and enable more granular control over the die stack.
  • Technical Importance: This type of architecture is foundational to modern high-density, high-performance memory solutions like High Bandwidth Memory (HBM), which require sophisticated methods for managing communication within a vertical stack of memory chips (Compl. ¶31).

Key Claims at a Glance

  • The complaint asserts infringement of at least independent claim 1 (Compl. ¶39).
  • Claim 1 describes a DRAM package with:
    • Stacked DRAM dies, including a first and second plurality of dies.
    • Terminals for receiving command/address (C/A) signals and data signals.
    • Die interconnects, including TSVs, to conduct signals to and from the DRAM dies.
    • A control die coupled between the terminals and the stacked DRAM dies.
    • A specific interconnect configuration where certain C/A and data interconnects are in electrical communication with only the first plurality of DRAM dies, while others are in communication with only the second plurality.
    • First unidirectional interconnects for signals from the DRAM dies to the control die, and second unidirectional interconnects for signals from the control die to the DRAM dies.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 10,025,731 - “Memory Module And Circuit Providing Load Isolation And Noise Reduction”

The Invention Explained

  • Problem Addressed: As memory systems increase in speed and density, signal integrity becomes a critical problem. Signal reflections and other electrical noise can occur at the interfaces between a memory controller, a memory module, and the memory devices themselves, degrading performance and limiting data transfer rates (’731 Patent, col. 1:51-62).
  • The Patented Solution: The patent describes a memory module with a specialized circuit placed between the module’s edge connector and its memory devices. This circuit contains a set of "correction circuits," which include at least one "programmable impedance matching circuit." Critically, control circuitry on the module "dynamically" controls this impedance matching circuit based on which rank of memory devices is currently selected for communication, thereby optimizing signal integrity for the active signal path (’731 Patent, Abstract; col. 17:25-33).
  • Technical Importance: This technology is relevant for high-speed memory standards like DDR5, which operate at very high data rates and require advanced techniques such as on-die termination (ODT) and equalization to maintain signal quality (Compl. ¶¶ 36-37).

Key Claims at a Glance

  • The complaint asserts infringement of at least independent claim 1 (Compl. ¶52).
  • Claim 1 describes a memory module with:
    • A printed circuit board with an edge connector.
    • Multiple ranks of memory devices.
    • At least one circuit coupled between the connector and the memory devices.
    • This circuit includes a "set of correction circuits" configured to make corrections to signals.
    • Each correction circuit includes at least one "programmable impedance matching circuit."
    • Control circuitry that receives address and control signals and "dynamically" controls the programmable impedance matching circuit based on which of the multiple ranks is selected.
  • The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

  • The complaint identifies two categories of accused products:
    1. Accused HBM Products: Any Micron HBM3E and newer products (e.g., HBM4, HBM4e) (Compl. ¶32).
    2. Accused DDR5 Products: Any Micron DDR5 memory modules with Decision Feedback Equalizer (DFE) and On-Die Termination (ODT)/RTT circuitry, such as Micron's DDR5 RDIMMs and MRDIMMs (Compl. ¶34).

Functionality and Market Context

  • The Accused HBM Products are described as a high-speed memory technology that relies on vertically-stacked memory dies connected by through-silicon vias (TSVs) and managed by a logic interface die at the base of the stack (Compl. ¶¶ 31, 40, 43). The complaint positions these products as critical for "AI innovation" and other high-performance computing applications (Compl. ¶31). A product diagram from Micron's website shows a "HBM3E Cube" of stacked dies mounted next to a GPU (Compl. p. 14).
  • The Accused DDR5 Products are the latest generation of industry-standard dual in-line memory modules (DIMMs) (Compl. ¶¶ 34, 36). The complaint alleges these modules incorporate features such as DFE and programmable ODT to enhance signal integrity, which enables the higher data rates characteristic of the DDR5 standard (Compl. ¶¶ 36, 37). A photograph from a product brief shows Micron's DDR5 RDIMM and MRDIMM products (Compl. p. 15).

IV. Analysis of Infringement Allegations

’087 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
stacked DRAM dies including at least a first plurality of DRAM dies and a second plurality of DRAM dies... The Accused HBM Products include stacked DRAM dies (e.g., 8, 12, or 16 dies), which constitute a first and second plurality of dies. ¶40 col. 1:40-41
a control die coupled between the terminals and the stacked DRAM dies... The products include a "control die" (also known as a "buffer die" or "logic die") coupled between the package terminals and the stacked DRAM dies. ¶43 col. 2:8-13
die interconnects further include first unidirectional interconnects configured to conduct signals from one or more DRAM dies... to the control die... The products include unidirectional differential data strobes (RDQS_t/RDQS_c) that conduct signals from the DRAM dies to the control die. ¶47 col. 2:57-61
die interconnects further include second unidirectional interconnects configured to conduct signals from the control die to one or more DRAM dies... The products include unidirectional differential Write strobes (WDQS_t/WDQS_c) that conduct signals from the control die to the DRAM dies. ¶47 col. 2:62-66
the control die is configured to, in response to the first set of C/A signals, receive first signals associated with the memory read operation from a DRAM die... via the first unidirectional interconnects... The control die is configured to receive signals (e.g., RDQS_t/RDQS_c) from the DRAM dies in response to read commands. A diagram shows the HBM3E cube with labeled TSVs facilitating vertical communication (Compl. p. 18). ¶47 col. 10:1-12
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the industry-standard HBM architecture, with its "logic die" and unidirectional data strobes (RDQS/WDQS), meets the specific claim limitations of a "control die" and distinct "first and second unidirectional interconnects." The analysis may focus on whether the functions of the accused logic die and data strobes map directly onto the functions recited in the patent's claims.
    • Technical Questions: What evidence does the complaint provide to support the allegation that specific interconnects are electrically connected to a first plurality of DRAM dies but "not in electrical communication with any... of the second plurality of DRAM dies" as claimed? The complaint alleges this configuration exists but provides visual evidence that may require expert analysis to confirm the precise electrical pathways (Compl. ¶¶ 44-45).

’731 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a plurality of memory devices on the printed circuit board, the plurality of memory devices being arranged in multiple ranks... The accused DDR5 RDIMMs comprise multiple Micron DDR5 SDRAMs arranged in multiple ranks. A functional block diagram shows a memory module with Rank 0 and Rank 1 (Compl. p. 26). ¶54 col. 6:1-6
at least one circuit coupled between the at least one connector and the plurality of memory devices... The accused DDR5 RDIMMs include circuits, such as DFE and ODT/RTT circuits, coupled between the edge connector and the memory devices. ¶¶ 55-56 col. 4:46-50
each circuit of the at least one circuit further comprising a set of correction circuits... The collection of the DFE and ODT/RTT circuits forms a set of correction circuits configured to make corrections in transmitted signals. A diagram illustrates a memory subsystem with a DFE circuit on the device (Compl. p. 27). ¶¶ 55-56 col. 10:39-43
the each correction circuit of the set of a correction circuits including at least one programmable impedance matching circuit... Each correction circuit, such as the ODT/RTT circuits, includes a programmable impedance matching circuit. ¶56 col. 10:44-48
control circuitry... further configured to dynamically control the at least one programmable impedance matching circuit... based on which of the multiple ranks is selected... The control circuitry is configured to dynamically control the ODT/RTT circuit because the RTT value of the targeted rank is set based on address and control signals, such as chip select signals that determine the rank to be accessed. ¶57 col. 17:25-33
  • Identified Points of Contention:
    • Scope Questions: The dispute may turn on whether industry-standard features like Decision Feedback Equalization (DFE) and On-Die Termination (ODT) fall within the patent's definition of a "set of correction circuits" containing a "programmable impedance matching circuit."
    • Technical Questions: What is the specific mechanism by which the accused "control circuitry" is alleged to "dynamically control" the impedance matching? The complaint suggests it is based on the rank selection signals that are part of the standard DDR5 command protocol, which raises the question of whether this operational link satisfies the claim's requirement (Compl. ¶57).

V. Key Claim Terms for Construction

  • The Term: "programmable impedance matching circuit" (’731 Patent, Claim 1)
  • Context and Importance: This term is critical because the infringement allegation hinges on mapping this claim element to the accused DDR5 products' On-Die Termination (ODT/RTT) functionality (Compl. ¶56). Practitioners may focus on this term because its construction will determine whether a standard feature of modern DRAM (selectable termination resistance) is equivalent to the patented "correction circuit."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the element as providing "coarse correction of signal noise due to impedance mismatches" and includes a network of resistors that can be configured to provide programmable impedance matching (’731 Patent, col. 10:40-62). This could support an interpretation covering any circuit with selectable impedance values used to improve signal integrity.
    • Evidence for a Narrower Interpretation: Figure 5 of the patent depicts the circuit as a single programmable resistor (’731 Patent, Fig. 5). The abstract describes the "correction circuit" as reducing noise in signals "transmitted between the first set of ports and the second set of ports," which could be argued to require a circuit physically located between the connector and memory device ports, rather than on the memory die itself, as ODT is.
  • The Term: "control die" (’087 Patent, Claim 1)
  • Context and Importance: The complaint alleges that the "buffer die" or "logic die" found in Micron's HBM products is the claimed "control die" (Compl. ¶43). The outcome of the infringement analysis for the ’087 patent may depend on whether the functions of Micron's logic die align with the functions recited for the "control die" in claim 1.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent states that the control die may include memory cells and serve as an array die, or it may be a distinct element that does not include memory cells (’087 Patent, col. 2:7-13). This flexibility could support reading the term on various types of logic or buffer dies.
    • Evidence for a Narrower Interpretation: Claim 1 requires the "control die" to perform specific functions, such as receiving signals via "first unidirectional interconnects" and driving signals via "second unidirectional interconnects" (’087 Patent, col. 10:1-12). An interpretation may be sought that limits the term to a die that performs this exact set of claimed I/O functions, raising a technical question of whether the accused HBM logic die operates in precisely this manner.

VI. Other Allegations

  • Indirect Infringement: For both the ’087 and ’731 patents, the complaint alleges inducement by asserting that Defendants provide specifications, datasheets, and instruction manuals that encourage and facilitate infringing use by customers and end-users (Compl. ¶¶ 48, 58). It also alleges contributory infringement, stating the accused products have no substantial non-infringing use and are a material part of the patented inventions (Compl. ¶¶ 49, 59).
  • Willful Infringement: For the ’731 Patent, the complaint alleges pre-suit willfulness, stating Micron had actual knowledge of the patent no later than April 28, 2021, via a letter from Netlist (Compl. ¶28). For the ’087 Patent, the complaint alleges willfulness based on knowledge acquired at least as of the filing of the original complaint (Compl. ¶50).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of technical mapping: Does the architecture of industry-standard HBM products, with their "logic die" and unidirectional data strobes (RDQS/WDQS), map onto the specific claimed configuration of a "control die" and distinct "unidirectional interconnects" as recited in the ’087 patent, or are there material structural and functional differences?
  • A second central issue will be one of definitional scope: Do the standard DFE (Decision Feedback Equalizer) and ODT (On-Die Termination) features in accused DDR5 memory modules constitute the claimed "set of correction circuits" including a "programmable impedance matching circuit" that is "dynamically controlled" based on rank selection, as understood in the context of the ’731 patent?
  • A key evidentiary question will be one of circuit configuration: What evidence will be presented to prove the specific connectivity and, critically, the specific lack of connectivity between certain interconnects and distinct pluralities of DRAM dies within the accused HBM stacks, as required by the claims of the ’087 patent?