Netlist Inc v. Micron Technology Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Netlist, Inc. (Delaware)
  • Defendant: Micron Technology, Inc., Micron Semiconductor Products, Inc., Micron Technology Texas, LLC (Delaware, Idaho)
  • Plaintiff’s Counsel: McKool Smith, P.C.; Irell & Manella LLP
• Case Identification: 2:25-cv-00558, E.D. Tex., 05/19/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendants have committed acts of patent infringement in the district and maintain regular and established places of business there.
• Core Dispute: Plaintiff alleges that Defendant’s High Bandwidth Memory (HBM) products infringe a patent related to high-density, stacked-die memory packages.
• Technical Context: The technology concerns architectures for vertically stacked dynamic random-access memory (DRAM) dies, a key component for high-performance computing, artificial intelligence, and cloud-based applications where data bandwidth and power efficiency are critical.
• Key Procedural History: The complaint references a history of litigation between the parties, including prior jury verdicts in favor of Netlist against Micron and other industry participants for infringement of different patents. Plaintiff also notes what it characterizes as "retaliatory suits" filed by Micron in Idaho and preemptively seeks a declaratory judgment that the present lawsuit was not brought in bad faith.

Case Timeline

Date	Event
2010-11-03	’087 Patent – Earliest Priority Date
2022-03-14	’087 Patent – Application Filing Date
2023-04-21	Prior jury verdict against Samsung noted in complaint
2024-05-24	Prior jury verdict against Micron noted in complaint
2024-11-08	Prior jury verdict against Samsung noted in complaint
2025-05-19	Complaint Filing Date
2025-05-20	’087 Patent – Issue Date

II. Technology and Patent(s)-in-Suit Analysis

• Patent Identification: U.S. Patent No. 12,308,087, "Memory Package Having Stacked Array Dies and Reduced Driver Load," issued May 20, 2025.

The Invention Explained

• Problem Addressed: In conventional high-density memory packages with multiple stacked semiconductor dies, a single driver on a control die must send signals to all dies in the stack. This creates a significant electrical load, requiring larger, more power-hungry drivers that consume valuable space on the control die (’087 Patent, col. 2:26-34).
• The Patented Solution: The patent describes an architecture that partitions the electrical load. Instead of one set of interconnects and drivers serving all dies in a stack, the invention uses multiple, distinct sets of interconnects. Each set is responsible for communicating with only a specific subset of the stacked dies. For example, a first interconnect communicates with the bottom two dies, while a separate, second interconnect communicates with the top two dies, effectively halving the load on each driver (’087 Patent, Fig. 2; col. 5:40-66). This allows for smaller drivers, reducing power consumption and improving performance.
• Technical Importance: This load-reduction technique enables the creation of memory packages with higher die counts and greater density without the prohibitive power and size penalties of conventional designs (’087 Patent, col. 4:1-3).

Key Claims at a Glance

• The complaint asserts independent claim 1 and reserves the right to assert other claims (Compl. ¶14, ¶27).
• Essential elements of independent claim 1 include:
  • A DRAM package with stacked DRAM dies comprising a "first plurality" and a "second plurality" of dies.
  • Die interconnects, including Through-Silicon Vias (TSVs), that are partitioned into distinct sets.
  • A first Command/Address (C/A) interconnect that is in electrical communication with the first plurality of DRAM dies but not in electrical communication with any C/A port on the second plurality.
  • A second C/A interconnect that is in electrical communication with the second plurality of DRAM dies but not in electrical communication with any C/A port on the first plurality.
  • A similar partitioned structure for data interconnects, where a first data interconnect serves the first plurality of dies but not the second, and vice-versa.
  • A control die coupled to the terminals and stacked DRAM dies that manages signals through various conduits.
  • First and second "unidirectional interconnects" for conducting signals to and from the control die, with specific configurations for driving and receiving signals for memory read and write operations.

III. The Accused Instrumentality

Product Identification

• The accused instrumentalities are Micron’s High Bandwidth Memory (HBM) products, specifically including "any Micron HBM3E, and newer products (e.g., HBM4; HBM4e)" (Compl. ¶24).

Functionality and Market Context

• The accused HBM products are described as a type of high-speed memory technology that uses vertically stacked DRAM dies connected via TSVs (Compl. ¶23, ¶28). They are designed for data-intensive applications like cloud computing and AI and are allegedly compliant with JEDEC industry standards (Compl. ¶22, ¶25).
• The complaint alleges that these products include a stack of DRAM dies and a "control die (also known as a 'buffer die' or 'logic die')" at the base that functions as a logic interface (Compl. ¶31). A rendering in the complaint shows an accused HBM3E Cube mounted next to a GPU, illustrating the vertically stacked memory dies and TSVs passing through them (Compl. p. 12). The complaint alleges these products are commercially significant, with Micron itself promoting them as fueling "AI innovation at up to 30% lower power consumption" (Compl. ¶23).

IV. Analysis of Infringement Allegations

’087 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
stacked DRAM dies including at least a first plurality of DRAM dies and a second plurality of DRAM dies...	The Accused HBM Products include stacked DRAM dies (e.g., 8, 12, or 16 dies) which can be grouped into a first and second plurality.	¶28	col. 5:6-9
terminals including command and/or address (C/A) terminals and data terminals...	The Accused HBM Products include terminals for C/A and data signals and are configured to perform memory read and write operations in response to C/A signals, as illustrated by the JEDEC Standard No. 238A Command Truth Table.	¶29	col. 2:40-45
die interconnects including C/A interconnects and data interconnects...each...including one or more through silicon vias (TSVs)...	The Accused HBM Products include die interconnects, C/A interconnects, and data interconnects that use TSVs to conduct signals to and from the stacked DRAM dies.	¶30	col. 5:35-40
a control die coupled between the terminals and the stacked DRAM dies...	The Accused HBM Products include a control die (also known as a "buffer die" or "logic die") that includes a logic interface and is coupled to the terminals and stacked DRAM dies.	¶31	col. 6:26-34
wherein a first C/A interconnect...is in electrical communication with...the first plurality of DRAM dies and not in electrical communication with...any of the second plurality of DRAM dies;	The complaint alleges the Accused HBM Products have C/A interconnects in the claimed configuration, where a first C/A interconnect communicates with a first plurality and not the second, and a second C/A interconnect communicates with the second plurality and not the first.	¶32	col. 24:19-28
wherein a first data interconnect...is in electrical communication with...the first plurality of DRAM dies and not in electrical communication with...any of the second plurality of DRAM dies.	The complaint alleges the Accused HBM Products have data interconnects in the claimed configuration, where some TSVs appear to electrically connect to only a subset of dies while bypassing others.	¶33, ¶15	col. 24:30-40
wherein the control die is configured to...receive first signals associated with the memory read operation...via the first unidirectional interconnects, and...drive second signals associated with the memory write operation...via the second unidirectional interconnects.	The Accused HBM Products allegedly include first and second unidirectional interconnects (e.g., RDQS and WDQS strobes) and a control die configured to receive signals on the first set and drive signals on the second set, consistent with JEDEC standards.	¶35	col. 8:35-51

• Identified Points of Contention:
  • Scope Questions: A central dispute may arise over the claim terms "first plurality" and "second plurality" of DRAM dies. The case may turn on whether the standardized, monolithic stack of an HBM product can be conceptually divided into the patent’s claimed "pluralities," which require functionally and electrically separate communication pathways.
  • Technical Questions: The complaint's allegations regarding the segregated interconnects are stated without detailed supporting evidence (Compl. ¶32, ¶33). A key evidentiary question will be whether Netlist can demonstrate that a specific interconnect in a Micron HBM product is truly "not in electrical communication with" dies in another alleged group, as required by the negative limitations in claim 1. This level of proof may require circuit analysis beyond what is publicly available and could be a significant focus of discovery.

V. Key Claim Terms for Construction

• The Term: "...not in electrical communication with..." (e.g., "not in electrical communication with any C/A port on any of the second plurality of DRAM dies")

• Context and Importance: This negative limitation is fundamental to the patent's claimed invention of load partitioning and is the lynchpin of the infringement theory. Whether a standard HBM architecture, where TSVs may physically pass through all dies, meets this requirement of electrical isolation will be a critical issue.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: Plaintiff may argue the plain meaning only requires the absence of a functional signal connection. The specification describes how an interconnect can pass through a die via TSVs without enabling electrical communication, suggesting a functional rather than absolute physical separation is intended (’087 Patent, col. 7:25-31; col. 6:1-10).
  • Evidence for a Narrower Interpretation: Defendant may argue that "not in electrical communication" requires complete electrical isolation, free from effects like parasitic capacitance or crosstalk, which might exist if a TSV physically traverses a die even without a direct tap. They may point to embodiments like Figure 2, which depicts physically separate interconnect paths ("220a", "220b"), to argue for a stricter level of separation than may be present in the accused products.

• The Term: "control die"

• Context and Importance: The complaint equates Micron's "buffer die" or "logic die" with the claimed "control die" (Compl. ¶31). The functions of this component must align with the claim requirements for infringement.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent describes the control die as containing "conduits" and "drivers" and being coupled between the terminals and the stacked dies (’087 Patent, col. 24:10-12). Netlist will likely argue that Micron’s logic die, which it states includes a "logic interface die" (Compl. ¶31), performs these functions and thus meets the definition.
  • Evidence for a Narrower Interpretation: Micron may argue its logic die performs functions different from those explicitly required by the claim language, or that the specific coupling and conduit structures recited in claim 1[d] are not present in its architecture. The definition is tied to the specific functions and connections recited in the full claim.

VI. Other Allegations

• Indirect Infringement: The complaint focuses on allegations of direct infringement and does not plead specific facts to support claims for induced or contributory infringement.
• Willful Infringement: The complaint does not contain a formal count for willful infringement, but the prayer for relief requests a finding of willfulness and enhanced damages (Compl., Prayer for Relief ¶D, ¶E). The complaint’s recitation of extensive prior litigation between the parties may be used to argue that Defendant had knowledge of its alleged infringement, at least post-suit (Compl. ¶16).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of architectural mapping: Does the architecture of Micron's standardized HBM products, which are built to a general industry specification (JEDEC), contain the specific, partitioned signal-routing structure required by the claims? The case will likely hinge on whether the patent's bespoke configuration of segregated "pluralities" and dedicated interconnects can be found in a mass-market component.
• A key evidentiary question will be one of negative proof: Can Netlist produce technical evidence sufficient to prove the negative limitations of claim 1—specifically, that certain interconnects are "not in electrical communication with" certain die groups? This will require a detailed, circuit-level infringement analysis that goes beyond product datasheets and marketing materials.
• A central legal question will be one of claim scope: How will the court construe the term "not in electrical communication"? A functional definition may favor the patentee, while a requirement for complete physical and electrical isolation could present a significant hurdle to proving infringement.